JPH02116149A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02116149A
JPH02116149A JP26984488A JP26984488A JPH02116149A JP H02116149 A JPH02116149 A JP H02116149A JP 26984488 A JP26984488 A JP 26984488A JP 26984488 A JP26984488 A JP 26984488A JP H02116149 A JPH02116149 A JP H02116149A
Authority
JP
Japan
Prior art keywords
substrate
capacitor
deformation
trench
circumference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26984488A
Other languages
Japanese (ja)
Inventor
Norio Nakamura
典生 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26984488A priority Critical patent/JPH02116149A/en
Publication of JPH02116149A publication Critical patent/JPH02116149A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To provide a buffer against an external force applied to a semiconductor element and avoid the deformation of the element and facilitate extra-thin mounting by a method wherein a trench is provided in the circumference of the element when the element is mounted on a substrate. CONSTITUTION:When an element 4 such as a chip capacitor is mounted on the surface of a substrate 5, a trench 6 is provided in the circumference of the element 4. At that time, the trench 6 may be provided so as to surround the element 4 or may be provided partially. When a chip capacitor 7 is mounted on a substrate 8, for instance, trenches 9 for restriction relief are provided around the capacitor 7 except two bridging parts 10 along two directions in the circumference of the capacitor 7. With this constitution, even if an external force is applied along the direction of arrows 11 and deformation is created, the bridging parts 10 are mainly deformed elastically and the stress is not applied to the capacitor 7.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置の基板の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a substrate of a semiconductor device.

[従来の技術] カード型の機器にみられる様に電子機器の厚さは、薄形
化が求められた結果として基板実装部分の高さ制限も厳
しくなり、その目的の為従来技術では回路基板厚みを減
少させることが行なわれて[発明が解決しようとする課
題] しかし前述の従来技術では基板厚みを大幅に減らさざる
を得ないため曲げ剛性の低下が避けられず問題となって
いる。その為実際の使用時には外力によちて発生する変
形は著しく増大され実装ボンディング部に引き起こされ
る応力も著しく増大することからはんだ付は部、IOボ
ンディング部にはく離が多発することとなり、時には実
装される素子自体が破壊に至ることすらある。
[Conventional technology] As a result of the demand for thinner electronic devices, such as those seen in card-type devices, restrictions on the height of the board mounting portion have become stricter. [Problem to be Solved by the Invention] The thickness has been reduced [Problem to be Solved by the Invention] However, in the above-mentioned conventional technology, since the substrate thickness has to be significantly reduced, a decrease in bending rigidity is unavoidable, which poses a problem. Therefore, during actual use, the deformation caused by external force increases significantly, and the stress caused in the mounting bonding area also increases significantly, resulting in frequent peeling of the soldering area and IO bonding area, and sometimes the mounting The device itself may even be destroyed.

そこで本発明はこの様な問題点を解決するもので、その
目的とするところは信頼性の高い薄形の実装構造を実現
し、さらに小型薄形軽量の半導体装置を提供するところ
にある。
The present invention is intended to solve these problems, and its purpose is to realize a highly reliable and thin mounting structure and to provide a small, thin, and lightweight semiconductor device.

[課題を解決するための手段] 本発明の半導体装置は、実装素子が配設される基板を有
する半導体装置において、前記基板は配設される前記実
装素子の周辺に溝が形成されることを特徴とする。
[Means for Solving the Problems] A semiconductor device of the present invention includes a substrate on which a mounted element is disposed, wherein the substrate has a groove formed around the mounted element on which it is disposed. Features.

[実施例] 第3図は本発明による基板の構造を示す斜視図で以下詳
細に説明する。4は基板上に実装される素子で本図では
1例としてチップコンデンサとする。5は基板であり、
6は基板5の実装素子周囲に設けられた溝である。この
基板に外力が加わり変形特に曲げ変形が生じた場合、本
発明の実施例である溝5によってチップコンデンサ4周
囲の拘束が極めて緩和されていることにより溝5内側で
は殆んど変形が生じることなく従ってチップコンデンサ
4のはんだ付は部に生じる応力も充分許容限度内に抑え
られる。
[Example] FIG. 3 is a perspective view showing the structure of a substrate according to the present invention, which will be described in detail below. Reference numeral 4 denotes an element mounted on the substrate, and in this figure, a chip capacitor is taken as an example. 5 is a substrate;
Reference numeral 6 denotes a groove provided around the mounted element on the substrate 5. When an external force is applied to this board and deformation occurs, especially bending deformation, most of the deformation will occur inside the groove 5 because the groove 5 according to the embodiment of the present invention extremely relaxes the restraint around the chip capacitor 4. Therefore, the stress generated in the soldering portion of the chip capacitor 4 can be sufficiently suppressed within the permissible limits.

第4図は変形の主方向が決っている場合に有効な本発明
の他の実施例の概観図で、7は図6におけるチップコン
デンサ1に相当し、8は回路基板9は拘束緩和のための
溝でチップコンデンサ7の周囲を二方向の狭いはしわた
し部10を残してとりかこむ様に構成する。矢印11の
向きに力が働き変形が生じた場合チップコンデンサ7及
びその周囲に比べ充分゛剛性が低くなっている橋わたし
部10が主に弾性変形することによってチップコンデン
サ7及びそのはんだ付は部に生じる応力を軽減すること
ができる。また矢印12のように曲げモーメントが作用
した場合にも拘束の緩さによって応力の発生を抑えるこ
とができ、またねじりが生じた場合にも第4図の構造は
有効である。
FIG. 4 is an overview diagram of another embodiment of the present invention which is effective when the main direction of deformation is determined, in which 7 corresponds to the chip capacitor 1 in FIG. The groove is configured to surround the chip capacitor 7 with narrow border portions 10 in two directions left. When a force is applied in the direction of the arrow 11 and deformation occurs, the bridging portion 10 whose rigidity is sufficiently lower than that of the chip capacitor 7 and its surroundings is mainly elastically deformed, causing the chip capacitor 7 and its soldering to deform. It is possible to reduce the stress generated in Furthermore, even when a bending moment acts as shown by arrow 12, the generation of stress can be suppressed by the looseness of the restraint, and the structure shown in FIG. 4 is also effective when twisting occurs.

XC等の様に入出力が多数存在するために第4図10の
狭いはしわたし部が設けられない場合でもできうる限り
実装部分周囲の拘束を減らすことが大変形を受けるカー
ド型半導体装置等の薄形製品の信頼性を向上させるため
に有効で、第5図は本発明の実装素子にICを選んだ場
合の概観図である。16はフラットパッケージエC11
4は回路基板、15は拘束緩和のための溝である。本構
造によれば16の矢印の様に曲げモーメントが発生する
場合には第6図、第4図でみてきた様に充分な効果があ
ることから製品の主たる変形方向を考慮して曲げが矢印
16のように起こる様に溝15の向きを決定すればよい
。また本構造における実装素子及び実装形態は全く制限
を受けないのは言うまでもない。その例として第6図は
第2図の様に高さを低く抑えるための従来技術に対して
本発明を適用した時の概観図また第7図は第5図のフラ
ットパッケージエ015をチップオンボード17でおき
かえた場合の概観図である。
Even in cases where the narrow border section shown in FIG. 4 and 10 cannot be provided due to the presence of a large number of inputs and outputs, such as in an XC, it is important to reduce the restraint around the mounting part as much as possible, such as card-type semiconductor devices that are subject to large deformations. This is effective for improving the reliability of thin products, and FIG. 5 is an overview diagram when an IC is selected as the mounting element of the present invention. 16 is flat package E C11
4 is a circuit board, and 15 is a groove for relaxing restraint. According to this structure, when a bending moment occurs as shown by the arrow 16, there is a sufficient effect as seen in Figs. 6 and 4. Therefore, considering the main deformation direction of the product, bending is The direction of the groove 15 may be determined so that the groove 15 occurs as shown in 16. Further, it goes without saying that the mounting elements and the mounting form in this structure are not limited at all. As an example, FIG. 6 is an overview diagram when the present invention is applied to the conventional technology for keeping the height low as shown in FIG. 2, and FIG. It is an overview diagram when the board 17 is replaced.

実装素子に生じる変形及び応力を大幅に改善でき、それ
によって薄形基板実装の信頼性の向上と、さらなる超薄
形実装の実現に大きな貢献をすることは疑う余地がない
There is no doubt that the deformation and stress occurring in mounted elements can be significantly reduced, thereby making a significant contribution to improving the reliability of thin board mounting and realizing even more ultra-thin mounting.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術の第1の実施例を示す斜視図第2図は
従来技術の第2の実施例を示す斜視図。第3図は本発明
の第1の実施例を示す斜視図。 第4図は本発明の第2の実施例を示す斜視図。第5図は
本発明の第3の実施例を示す斜視図。第6図は本発明の
第4の実施例を示す斜視図。第7図は本発明の第5の実
施例を示す斜視図。 4.7,13.17・・・・・・素 子5.8,14 
   ・・・・・・基 板6.9,15  、  ・・
・・・・溝[発明の効果] 実装素子に加わる外力を緩衝する機構を基板にもつ本発
明によれば大変形をうける実装基板中の以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部(他1名)第3図 ′第4図
FIG. 1 is a perspective view showing a first embodiment of the prior art. FIG. 2 is a perspective view showing a second embodiment of the prior art. FIG. 3 is a perspective view showing the first embodiment of the present invention. FIG. 4 is a perspective view showing a second embodiment of the invention. FIG. 5 is a perspective view showing a third embodiment of the present invention. FIG. 6 is a perspective view showing a fourth embodiment of the present invention. FIG. 7 is a perspective view showing a fifth embodiment of the present invention. 4.7, 13.17... Element 5.8, 14
... Board 6.9, 15, ...
...Groove [Effect of the Invention] According to the present invention, the substrate has a mechanism for buffering the external force applied to the mounted elements, and the mounting board is subject to large deformation.Applicant: Seiko Epson Co., Ltd. Agent Patent Attorney Kizo Suzuki Department (1 other person) Figure 3' Figure 4

Claims (1)

【特許請求の範囲】[Claims] 実装素子が配設される基板を有する半導体装置において
前記基板は配設された前記実装素子の周辺に溝が形成さ
れることを特徴とする半導体装置
A semiconductor device having a substrate on which a mounted element is arranged, wherein the substrate has a groove formed around the mounted element.
JP26984488A 1988-10-26 1988-10-26 Semiconductor device Pending JPH02116149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26984488A JPH02116149A (en) 1988-10-26 1988-10-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26984488A JPH02116149A (en) 1988-10-26 1988-10-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02116149A true JPH02116149A (en) 1990-04-27

Family

ID=17477977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26984488A Pending JPH02116149A (en) 1988-10-26 1988-10-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02116149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104333978A (en) * 2014-10-20 2015-02-04 中山市惠亚线路版有限公司 Circuit board tin spraying pretreatment method and circuit board before tin spraying

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104333978A (en) * 2014-10-20 2015-02-04 中山市惠亚线路版有限公司 Circuit board tin spraying pretreatment method and circuit board before tin spraying

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