JPH02110343U - - Google Patents
Info
- Publication number
- JPH02110343U JPH02110343U JP1970589U JP1970589U JPH02110343U JP H02110343 U JPH02110343 U JP H02110343U JP 1970589 U JP1970589 U JP 1970589U JP 1970589 U JP1970589 U JP 1970589U JP H02110343 U JPH02110343 U JP H02110343U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- insulating layer
- copper foil
- rolled copper
- aluminum plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011889 copper foil Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000004382 potting Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の半導体装置の一実施例の断面
図及び下面図、第２図は本考案の半導体装置を実
装基板に取付けた場合の斜視図、第３図は従来の
半導体装置の一例の斜視図及び断面図である。
１……半導体チツプ、１０……アルミ基板、２
……アルミ板、３……絶縁層、４……圧延銅箔、
５……リード線、６……保護用樹脂。
Figure 1 is a sectional view and bottom view of an embodiment of the semiconductor device of the present invention, Figure 2 is a perspective view of the semiconductor device of the present invention mounted on a mounting board, and Figure 3 is an example of a conventional semiconductor device. FIG. 2 is a perspective view and a cross-sectional view. 1... Semiconductor chip, 10... Aluminum substrate, 2
... Aluminum plate, 3 ... Insulating layer, 4 ... Rolled copper foil,
5... Lead wire, 6... Protective resin.
Claims (1)
、更にこの絶縁層の上にその中央部を除いて圧延
銅箔を密着しこの圧延銅箔にその周辺から端部に
至るリード端子をパターニングにより形成しかつ
前記アルミ板を外向きにして凸型に成形してなる
アルミ基板と、 前記アルミ基板の内側で圧延銅箔の形成が除か
れてある中央部にダイボンデイングにより固着さ
れた半導体チツプと、 前記半導体チツプと前記リード端子とをワイヤ
ボンデイングで接続するリード線と、 前記半導体チツプをポツテイングによりカバー
してなる保護用樹脂と、 を備えることを特徴とする半導体装置。[Claim for Utility Model Registration] An insulating layer is placed on top of a heat sink made of an aluminum plate, and further a rolled copper foil is adhered onto this insulating layer except for the center part, and the rolled copper foil is coated from the periphery to the edge. An aluminum substrate is formed by patterning lead terminals leading to the ends of the aluminum substrate, and is formed into a convex shape with the aluminum plate facing outward; A semiconductor device comprising: a fixed semiconductor chip; a lead wire connecting the semiconductor chip and the lead terminals by wire bonding; and a protective resin covering the semiconductor chip by potting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1970589U JPH02110343U (en) | 1989-02-22 | 1989-02-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1970589U JPH02110343U (en) | 1989-02-22 | 1989-02-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02110343U true JPH02110343U (en) | 1990-09-04 |
Family
ID=31235452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1970589U Pending JPH02110343U (en) | 1989-02-22 | 1989-02-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02110343U (en) |
-
1989
- 1989-02-22 JP JP1970589U patent/JPH02110343U/ja active Pending