JPH0189789U - - Google Patents
Info
- Publication number
- JPH0189789U JPH0189789U JP1987185525U JP18552587U JPH0189789U JP H0189789 U JPH0189789 U JP H0189789U JP 1987185525 U JP1987185525 U JP 1987185525U JP 18552587 U JP18552587 U JP 18552587U JP H0189789 U JPH0189789 U JP H0189789U
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- integrated circuit
- hybrid integrated
- circuit device
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims 2
- 230000001681 protective effect Effects 0.000 claims 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
第１図ａ，ｂはそれぞれ本考案の第一の実施例
を説明するための混成集積回路装置の斜視図およ
びＡ―Ａ′線断面図、第２図ａ，ｂはそれぞれ本
考案の第二の実施例を説明するための混成集積回
路装置の斜視図およびＢ―Ｂ′線断面図、第３図
ａ，ｂはそれぞれ従来の一例を説明するための混
成集積回路装置の斜視図およびＣ―Ｃ′線断面図
である。
１……回路基板、２……放熱板、３……放熱板
位置決めパターン、４……外部リード、５……接
着樹脂材、６……接続導体、７……パワーチツプ
、８……ボンデイングワイヤ、９……電子部品、
１０……外部樹脂、１１……放熱板凹部。
1A and 1B are a perspective view and a sectional view taken along the line A-A' of a hybrid integrated circuit device for explaining the first embodiment of the present invention, respectively, and FIGS. FIGS. 3a and 3b are a perspective view and a sectional view taken along the line B-B' of a hybrid integrated circuit device for explaining an example of the conventional hybrid integrated circuit device, and FIGS. It is a sectional view taken along the line C'. DESCRIPTION OF SYMBOLS 1... Circuit board, 2... Heat sink, 3... Heat sink positioning pattern, 4... External lead, 5... Adhesive resin material, 6... Connection conductor, 7... Power chip, 8... Bonding wire, 9...Electronic parts,
10... External resin, 11... Heat sink recess.
Claims (1)
とは反対の面に樹脂により放熱板を接着する混成
集積回路装置において、前記回路基板の放熱板取
り付け面側に絶縁ガラス又は保護ガラスにより位
置決めパターンを被着したことを特徴とする混成
集積回路装置。 In a hybrid integrated circuit device in which a power chip is mounted on a circuit board and a heat sink is bonded with resin to the surface opposite to the mounting surface, a positioning pattern is covered on the heat sink mounting surface of the circuit board with insulating glass or protective glass. A hybrid integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987185525U JPH0189789U (en) | 1987-12-04 | 1987-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987185525U JPH0189789U (en) | 1987-12-04 | 1987-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0189789U true JPH0189789U (en) | 1989-06-13 |
Family
ID=31476839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987185525U Pending JPH0189789U (en) | 1987-12-04 | 1987-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0189789U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03194957A (en) * | 1989-12-21 | 1991-08-26 | Internatl Business Mach Corp <Ibm> | Plastic-chip circuit package, method of reinforcing heat dissipation of electronic part and method of mounting heat-sink-element |
-
1987
- 1987-12-04 JP JP1987185525U patent/JPH0189789U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03194957A (en) * | 1989-12-21 | 1991-08-26 | Internatl Business Mach Corp <Ibm> | Plastic-chip circuit package, method of reinforcing heat dissipation of electronic part and method of mounting heat-sink-element |