JPH02105622A - Logic gate circuit - Google Patents

Abstract

PURPOSE:To drive a load larger than ever before without increasing a delay time by connecting a bipolar transistor to drive the load of an output terminal in a compound logic gate circuit consisting of a CMOS to an output side. CONSTITUTION:The output of the compound logic gate circuit 11 consisting of the CMOS is connected to the base of a first NPN-type bipolar transistor 13. A partial circuit consisting of an N-channel transistor in the compound logic gate circuit 11 and a circuit 12 having the same circuit connection are connected between the collector and the base of a second NPN-type bipolar transistor 14, and the first and second NPN-type bipolar transistors are cascade- connected. In such a way, it is possible to reduce the load dependency of the delay time by connecting the NPN-type bipolar transistors 13 and 14, and to drive the load larger than ever before without increasing the delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic gate circuit, and particularly to a logic gate circuit having complementary MOS transistors and bipolar transistors.

[Conventional technology]

Conventionally, logic gate circuits are composite logic gate circuits created for the purpose of reducing delay time. Next, a typical conventional example of this composite logic gate circuit will be shown, and its construction and operation will be explained with reference to FIG.

FIG. 3 is a circuit diagram of a three-man power composite logic gate circuit composed of 0MO8. In FIG. 3, the three-manpower composite logic gate circuit of this embodiment has input terminals 39, 40, and further includes P-channel type MOS transistors 33, 35, and N
2 having channel type MOS transistors 34 and 36
Manual NOR gate and input terminal 41. P channel type MO
8) A gate circuit 31 consisting of a run raster 3 and a NOR gate having an N channel type MOS transistor 38, 0MOS transistors 42, 43, and an output pin 44.
The inverter 32 has an inverter 32.

That is, by combining two NAND gates and a NOR gate, a circuit consisting of two stages of gates can be realized in one stage, and it is a logic gate circuit aiming at a single line delay time. Generally, when a logic gate circuit has a large load capacitance attached to its output terminal, it is common to attach a driving inverter above the setup to the output terminal. The gate circuit shown in FIG. 3 includes a composite logic gate circuit 31 of NAND and NOR.
This is an example of driving with a stage inverter 32.

In such a composite logic gate circuit, the delay time increases in proportion to the number of driving inverter stages and the load capacitance of the output terminal. In the case of a composite logic gate circuit configured with 0MO8, the delay time has a large dependence on the output load, so as the output load increases, the delay time increases significantly. Also,
In order to drive a large output load, increasing the number of stages of driving inverters has the drawback of increasing delay time.

[An ode that the invention attempts to solve]

The conventional composite logic gate circuit described above has an output terminal (
If the stuck load capacity is large, there is a drawback that a large increase in delay time is unavoidable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic gate circuit that solves the above-mentioned drawbacks, reduces delay time, and performs high-speed logic operation.

[Measures to Solve the Problem] The configuration of the present invention is such that, in a logic gate circuit including a composite logic gate composed of complementary MOS transistors, the output of the composite logic gate is connected to an output terminal for driving a load. The feature is that a bipolar transistor is provided between them.

〔Example〕

Next, non-invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram showing a logic gate circuit according to a first embodiment of the present invention. In FIG. 1, the logic gate circuit of this embodiment is a composite logic gate circuit 11 composed of 0MO8.
The output of the first NPN bipolar transistor 130
N of the composite logic gate circuit 11 is connected to the base.
A circuit 12 having the same circuit connection as a partial circuit constituted by a channel type transistor is connected between the collector and the pace of the second NPN type bipolar transistor 14, and the circuit 12 has the same circuit connection as the partial circuit made up of the channel type transistor. The transistors were connected vertically.

The circuit 11 is a composite logic gate circuit that combines a two-man power NAND gate and a NOR gate like the circuit 31 and II'-j in FIG.
', 36', and 38' have the same circuit configuration as the portion of the circuit 11 consisting of N-channel MOS transistors 34, 36, and 38. In this embodiment, in addition to the above, N-channel type MO8) Kunraster 16 bibolar transistors 13, 14 . It includes an output terminal 15.

In this embodiment, the output of the circuit 11 is connected to the base of an NPN bipolar transistor 130, the circuit 12 is connected between the collector and base of the NPN bipolar transistor 14, and the NPN bipolar transistors 13 and 14 are connected in cascade. It is a connected logic gate circuit.

In the conventional composite logic gate circuit configured with 0MO8, NPN bipolar transistors 13.
By connecting 14, the dependence of the delay time on the load can be reduced, and it is possible to drive a larger load without increasing the delay time.

FIG. 2 is a circuit diagram showing a logic gate circuit according to a second embodiment of the present invention. In FIG. 2, the present embodiment has two human power N of the circuit 11 in the first embodiment (FIG.
A composite logic gate circuit with an OR gate and a NOR gate,
Replaced with a composite logic gate circuit of a two-man power NOR gate and a NAND gate shown in circuit 21, and following this, the first
The circuit 12 in the figure is an N-channel MOS transistor S/
, 9/.

This is a logic gate circuit replaced with the circuit 22 consisting of lO'. The circuit 21 has input terminals 1.2. P channel type NO
8) Run raster 5.6. A two-man NOR gate having N-channel type MOS transistors 8, 9, and 10, and an input terminal 3. P channel type MOS? 7. It consists of a NAND gate having an N-channel type MOS transistor 10.

In this embodiment as well, as in the first embodiment, it is possible to drive a larger output load, although this involves an increase in delay time.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by connecting a bipolar transistor to the output side for driving the load of the output terminal of a composite logic gate circuit configured with 0MO8, the delay time can be further improved without increasing the delay time. It has the ability to drive large loads.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a logic gate circuit according to a first embodiment of the invention, FIG. 2 is a circuit diagram showing a logic gate circuit according to a second embodiment of the invention, and FIG. 3 is a circuit diagram showing a logic gate circuit according to a second embodiment of the invention. FIG. 2 is a circuit diagram showing a gate circuit. 1.2, 3.39, 40.41... Input terminal,
4.15.44... Output terminal, 5, 6, 7, 3
3゜35.37.42...P channel type MOS
Transistor, 8.9, 10.8', 9', 10', I
6゜23, 34.36, 38.43.34', 36
', 38'...N-channel type MO3) transistor, 11.31...NAND-NOR composite logic gate circuit, 12P22.32...Circuit, 13
．． 14...NPN type transistor, 21...
...N0R-NAND composite logic gate circuit. Agent: Patent Attorney Go Uchihara

Claims (1)

[Claims] A logic gate circuit including a composite logic gate composed of complementary MOS transistors, characterized in that a bipolar transistor is provided between the output of the composite logic gate and an output terminal for driving a load. circuit.