JPH05268052A - Tri-state buffer circuit - Google Patents

Abstract

PURPOSE:To improve the drive capacity of the tri-state buffer circuit and to attain high speed processing through the reduction in the number of logic stages. CONSTITUTION:Two bipolar transistors(TRs) are connected in series between a high potential Vcc and a low potential power supply of an output stage, an AND signal between an input signal IN and a control signal CONT drives an NPN transistor(TR) 17, a P-channel MOS TR 15 is turned on only when the input signal IN is at logical 0 and the control signal CONT is at logical 1, and an NPN TR 18 is driven. Thus, a large capacity load is driven with a small area by using a bipolar transistor (TR) for an output stage, the number of logic stages is reduced more than that of a conventional circuit and a delay time from the input to the output is reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a three-state buffer circuit.

[0002]

2. Description of the Related Art Conventionally, there is a 3-state buffer circuit of this type as shown in FIG.

P-channel MOSF for driving a load
The ET 36 and the N-channel MOSFET 39 are connected in series from high potential to low potential, and the input (IN) signal of the input terminal and the control (CONT) signal of the control terminal are connected to the NAND gate 33.
In addition to the output of the NAND gate 33,
In addition to the gate of the P-channel MOSFET 36 through two stages of 35, an inverted signal of the input (IN) signal and the control (CONT) signal is added to the NOR gate 32, and the NOR gate 32
Is applied to the gate of the N-channel MOSFET 39 through the two stages of the inverters 37 and 38.

This circuit, as shown in the truth table of FIG.
When the control signal CONT has a low potential (hereinafter abbreviated as “0”), the output OUT has a high impedance (hereinafter abbreviated as “Z”) and the control signal CONT has a high potential (hereinafter “1”).
Abbreviated), the input signal IN is transmitted to the output OUT.

[0005]

Since the above-mentioned conventional circuit uses the MOSFETs 36 and 39 in the output stage,
It requires a large-area transistor and has a large output capacitance. Further, the gate capacity is also considerably large, and in order to drive this, a buffer of about two stages of inverters is required, and the number of logic stages from the input to the output is large and the delay time becomes large.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a three-state buffer circuit having a reduced delay time.

[0007]

The structure of the three-state buffer circuit of the present invention is such that the first series body of the first and second bipolar transistors is connected between the first and second constant power sources.
A common connection point of the first series body is connected to an output terminal, a second series body of the first and second field effect transistors is connected between bases of the first and second bipolar transistors, and A common connection point of the second series body is connected to the output terminal, a third field effect transistor is connected between the first constant power source and the gate of the second field effect transistor, and an input terminal is connected. A fourth field effect transistor is connected between the base of the first bipolar transistor and a fifth field effect transistor is connected between the input terminal and the gate of the second field effect transistor. ,
The gates of the first, third, fourth and fifth field effect transistors are connected to a control terminal, and a resistor or a field effect transistor is provided between the base of the second bipolar transistor and the second constant power source. It is characterized by intervening.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a three-state circuit of the first embodiment of the present invention.
It is a circuit diagram showing a buffer circuit.

Referring to FIG. 1, the buffer circuit of this embodiment has an input terminal 50, a control terminal 51, and an N-channel MO.
S field effect transistors (FET) 11 and 12, P channel MOSFETs 13, 14 and 15, a resistor 16, and
It is provided with NPN bipolar transistors 17 and 18, a high potential (Vcc) terminal 60, an output (OUT) terminal 62, and a low voltage terminal 61.

Base of transistor 17 and input terminal 50
FET11 is interposed between
8 is connected in series, the common connection point is the output terminal 62, the FETs 14 and 15 are connected in series between the bases of the transistors 17 and 18, the common connection point is the output terminal 62, and the control terminal 51 is the FET 11, FET12 is connected between the input terminal 50 and the gate of the FET15, the FET13 is connected between the gate of the FET15 and the high potential terminal 60, and the base of the transistor18 and the low potential are connected. The resistor 16 is connected to the voltage terminal 61.

That is, in the buffer circuit of this embodiment, the input signal is supplied to the source of the first N-channel MOSFET 11 and the second signal.
A source of the N-channel MOSFET 12 and a control signal to the first N-channel MOSFET 11 and the second N-channel MOSFET 12 and the first P-channel M.
In addition to the respective gates of the OSFET 13 and the second P-channel MOSFET 14, the first P-channel MOS
The source of the FET 14 is connected to a high potential, the drain of the first N-channel MOSFET 11 and the source of the second P-channel MOSFET 14 are connected to the base of the first NPN transistor 17, and the first NPN type is connected. The collector of the transistor 17 is connected to a high potential, and the second
The drain of the N-channel MOSFET 12 and the drain of the first P-channel MOSFET 13 are connected to the gate of the third P-channel MOSFET 15, and the drain of the third P-channel MOSFET 15 is connected to the second
Of the second NPN transistor 18 is connected to the base of the second NPN transistor 18 through a load element to a low potential, and the emitter of the second NPN transistor 18 is connected to a low potential. 1 NPN
-Type transistor 17 emitter, the second P-channel MOSFET 14 drain and the third P-channel M
The source of the OSFET 15 and the collector of the second NPN transistor 18 are connected to each other to form an output terminal.

Referring to FIG. 1, in this embodiment, two bipolar transistors 17 and 18 are connected in series between Vcc and a low potential in the output stage, and when the NPN transistor 17 is turned on, the output OUT is "1". When the NPN transistor 18 is turned on, the output OUT is "0", and when both transistors are off, the output OUT is "Z".

AN of input signal IN and control signal CONT
The D signal drives the NPN transistor 17, the P-channel MOSFET 15 is turned on when the input signal IN is "0" and the control signal CONT is "1", and the NPN transistor 18 is driven. The output OUT of the resistor 16 is “0”
The base electric charge of the NPN type transistor 18 is discharged when it changes from "1" to "1".

Next, the operation will be described in detail with reference to the truth table of FIG. When the control signal CONT is “0”, the input signal I
Regardless of N, N-channel MOSFET 11 is off, P
Since the channel MOSFET 14 is turned on, the base charge of the NPN transistor 17 is discharged and turned off. Since the N-channel MOSFET 12 is turned off and the P-channel MOSFET 13 is turned on, the level at the point B becomes "1", the P-channel MOSFET 15 is turned off and the NPN transistor 18 is turned off. Therefore,
The output OUT becomes "Z".

When the input signal IN is "0", the control signal CONT
Is "1", the N-channel MOSFET 11 is on and P
Since the channel MOSFET 14 is turned off, the level at point A becomes "1" and the NPN transistor 17 is turned off. Since the N-channel MOSFET 12 is turned on and the P-channel MOSFET 13 is turned off, the level at the point B becomes "0", the P-channel MOSFET 15 is turned on and the NPN type transistor 18 is turned on. Therefore, the output OUT becomes "0".

When the input signal IN is "1", the control signal CONT
Is "1", the N-channel MOSFET 11 is on and P
Since the channel MOSFET 14 is turned off, the level at point A becomes "1" and the NPN transistor 17 is turned on. In addition, the N-channel MOSFET 12 is turned on and P
Since the channel MOSFET 13 is turned off, the point B becomes "1", the P-channel MOSFET 15 is turned off, and the NPN transistor 18 is turned off. Therefore,
The output OUT becomes "1". Thus, the circuit of FIG. 1 operates as a 3-state buffer circuit.

FIG. 3 is a circuit diagram showing a 3-state buffer circuit according to the second embodiment of the present invention.

In FIG. 3, the buffer circuit of the present embodiment has an N-channel MOS instead of the resistor 16 of the circuit of FIG.
The FET 26 is used. The gate of the FET 26 is connected to the output terminal. The other parts are the same as those in FIG.

In the operation of FIG. 3, as shown in the truth table of FIG. 4, the input signal IN is "1" and the control signal CONT is "1".
Output OUT becomes "1" at the time of, and N channel MOSF
The ET 26 is turned on to discharge the base charge of the NPN transistor 28. Otherwise, N channel M
The OSFET 26 is off.

[0020]

As described above, according to the present invention, by using a bipolar transistor in the output stage, a large capacity load can be driven in a small area, and the number of logic stages and the number of elements can be reduced as compared with the conventional example. There is an effect that it can be reduced and the delay time from input to output can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a state buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a truth table for explaining the circuit operation of FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a diagram showing a truth table for explaining the circuit operation of FIG. 3;

FIG. 5 is a circuit diagram of a conventional 3-state buffer circuit.

FIG. 6 is a diagram showing a truth table for explaining the circuit operation of FIG. 5;

[Explanation of symbols]

IN input signal CONT control signal Vcc high potential OUT output signal 31, 34, 35, 37, 38 inverter 33 2 input NAND gate 32 2 input NOR gate 13, 14, 15, 23, 24, 25, 36 P-channel MOSFET 11, 12, 21, 22, 26, 39 N channel M
OSFET 17, 18, 27, 28 NPN type transistor 16 Resistance 50 Input terminal 51 Control terminal 60 High potential terminal 61 Low potential terminal 62 Output terminal

Claims (1)

[Claims] 1. A first series body of first and second bipolar transistors is connected between a first and a second constant power source, and a common connection point of the first series body is connected to an output terminal, Between the bases of the first and second bipolar transistors,
Connecting a second series body of a second field effect transistor,
A common connection point of the second series body is connected to the output terminal, a third field effect transistor is connected between the first constant power source and the gate of the second field effect transistor, and an input terminal is connected. And a base of the first bipolar transistor, a fourth field effect transistor is connected between the input terminal and a gate of the second field effect transistor, and a fifth field effect transistor is connected between the input terminal and the gate of the second field effect transistor. Then
The gates of the first, third, fourth and fifth field effect transistors are connected to a control terminal, and a resistor or a field effect transistor is provided between the base of the second bipolar transistor and the second constant power source. A 3-state buffer circuit characterized by being interposed.