JPH01181320A - Noise reduction type input drive circuit - Google Patents
Noise reduction type input drive circuitInfo
- Publication number
- JPH01181320A JPH01181320A JP63005917A JP591788A JPH01181320A JP H01181320 A JPH01181320 A JP H01181320A JP 63005917 A JP63005917 A JP 63005917A JP 591788 A JP591788 A JP 591788A JP H01181320 A JPH01181320 A JP H01181320A
- Authority
- JP
- Japan
- Prior art keywords
- drive circuit
- output
- input
- terminal
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路における入力信号の雑音減少化
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to noise reduction of input signals in semiconductor integrated circuits.
従来の絶縁ゲート電界効果型トランジスタ（以下Ｍ Ｏ
Ｓ Ｆ Ｆ、 Ｔと略す）を用いた入力駆動回路は第３
図に示すように、入力端子３０から入力された信号が入
力保護ダイオード３１．３２を通り、ソース電極を＋Ｖ
ｏｏに接続したＰ型Ｍ ＯＳ Ｆ Ｅ Ｔ３３と、ソー
ス電極を−ｖｓｓに接続したＮ型ＭＯＳＦＥＴ３４のゲ
ート電極に入力され、その出力は、ソース電極を＋ＶＯ
Ｏに接続したＰ型Ｍ ＯＳ ＦＥＴ３５と、ソース電極
を−ＶＳＳに接続したＮ型Ｍ ＯＳ Ｆ Ｂ ７３６の
ゲート電極に入力し、その出力を内部信号へ伝える構成
となっていた。Conventional insulated gate field effect transistor (hereinafter referred to as MO
The input drive circuit using the SFF, abbreviated as T is the third
As shown in the figure, the signal input from the input terminal 30 passes through the input protection diodes 31 and 32, and the source electrode is connected to +V.
The output is input to the gate electrode of the P-type MOSFET33 connected to oo and the N-type MOSFET34 whose source electrode is connected to -vss, and its output is
The configuration was such that the output was inputted to a P-type MOS FET 35 connected to O and a gate electrode of an N-type MOS FET 736 whose source electrode was connected to -VSS, and the output thereof was transmitted to an internal signal.
しかし、前述の従来技術では、前記第３図に示す入力保
護ダイオード３１．３２の能力以上の電流、または雑音
が生じると、入力保護ダイオードだけでは保護できず、
内部信号へ悪影響を与えるという問題があった。However, in the prior art described above, when a current or noise exceeding the capacity of the input protection diodes 31 and 32 shown in FIG. 3 occurs, the input protection diodes alone cannot provide protection.
There was a problem that it adversely affected internal signals.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは入力信号に生じる雑音を減少させ
、雑音の少ない内部信号を生成する雑音減少型入力駆動
回路を提供することである。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a noise reduction type input drive circuit that reduces the noise generated in an input signal and generates an internal signal with less noise. .
本発明の雑音減少型入力駆動回路は、
ａ）ＭＯＳＦＥＴを用いた半導体集積回路において、
ｂ）正極の電源端子にソース電極を接続したＰ型Ｍ Ｏ
Ｓ Ｆ Ｅ Ｔと、負極の電源端子にソース電極を接続
したＮ型ＭＯＳＦＥＴを少なくとも具備し、ｃ）Ｐ型Ｍ
ＯＳ Ｆ Ｅ Ｔと、Ｎ型ＭＯＳＦＥＴのそれぞれの
ドレイン電極を互いに接続し、前記Ｐ型Ｍ ＯＳ Ｆ
Ｅ Ｔと前記Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極
を互いに接続した第１の駆動回路を少なくとも具備した
入力駆動回路と
ｄ）Ｐ型ＭＯＳ Ｆ Ｅ ＴとＮ型ＭＯＳＦＥＴのそれ
ぞれのドレイン電極を互いに接続し、前記Ｐ型ＭＯＳＦ
ＥＴと前記Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極を
互いに接続した第２の駆動回路と出力制御回路からなる
出力駆動回路を使用し、ｅ）前記入力駆動回路と前記出
力駆動回路で構成された入出力駆動回路の出力駆動回路
の出力制御端子及び内部出力端子を＋ｖＩ）Ｄまたは−
ＶＨに固定することを特徴とする。The noise reduction type input drive circuit of the present invention includes: a) a semiconductor integrated circuit using a MOSFET; b) a P-type MOSFET in which a source electrode is connected to a positive power supply terminal;
S FET, and at least an N-type MOSFET whose source electrode is connected to the negative power supply terminal, and c) P-type MOSFET.
The respective drain electrodes of the OS FET and the N-type MOSFET are connected to each other, and the P-type MOSFET
d) an input drive circuit comprising at least a first drive circuit in which the respective gate electrodes of the P-type MOSFET and the N-type MOSFET are connected to each other; and d) the respective drain electrodes of the P-type MOSFET and the N-type MOSFET are connected to each other. , the P-type MOSF
an output drive circuit consisting of a second drive circuit and an output control circuit in which gate electrodes of the ET and the N-type MOSFET are connected to each other; e) an input/output circuit consisting of the input drive circuit and the output drive circuit; Output of the drive circuit Connect the output control terminal and internal output terminal of the drive circuit to +vI)D or -
It is characterized by being fixed to VH.
上記の構成による入力駆動回路を動作すると、＋ Ｖ
ＤＤに接続された出力駆動回路により、出力駆動部分の
トランジスタは０ＦＦＬ、出力駆動部分が保護ダイオー
ドとなる°ため、入力信号の雑音を小さくすることがで
きるのである。When the input drive circuit with the above configuration is operated, +V
Due to the output drive circuit connected to the DD, the transistor in the output drive section is set to 0FFL, and the output drive section becomes a protection diode, so that the noise of the input signal can be reduced.
以下に本発明の実施例を図面にもとづいて説明する。第
１図において破線１で囲まれた回路が入力駆動回路であ
り、破線２で囲まれた回路が出力駆動回路であり、破線
３で囲まれた回路が出力制御回路である。入力駆動回路
１において、Ｐ型ＭＯＳＦＥＴ１３のソース電極は＋Ｖ
ＤＤに接続されＮ型ＭＯＳＦＥＴ１４のソース電極は−
Ｖ＃８に接続され、Ｐ型ＭＯ３ＦＥ７１３とＮ型ＭＯＳ
ＦＥＴ１４のゲート電極は互いに接続して入力端子１０
に接続されている。Ｐ型ＭＯ３ＦＥ７１３とＮ型ＭＯＳ
ＦＥＴ１４のドレイン電極は互いに接続され、ソース電
極を＋ＶＯＯに接続したＰ型ＭＯＳＦＥＴ１５とソース
電極を一■ｓ、に接続したＮ型Ｍ ＯＳ Ｆ Ｅ Ｔ
１６のゲート電極に接続されている。Embodiments of the present invention will be described below based on the drawings. In FIG. 1, the circuit surrounded by a broken line 1 is an input drive circuit, the circuit surrounded by a broken line 2 is an output drive circuit, and the circuit surrounded by a broken line 3 is an output control circuit. In the input drive circuit 1, the source electrode of the P-type MOSFET 13 is +V
The source electrode of the N-type MOSFET 14 connected to DD is -
Connected to V#8, P type MO3FE713 and N type MOS
The gate electrodes of the FETs 14 are connected to each other and connected to the input terminal 10.
It is connected to the. P-type MO3FE713 and N-type MOS
The drain electrodes of the FET 14 are connected to each other, the P-type MOSFET 15 has its source electrode connected to +VOO, and the N-type MOSFET 15 has its source electrode connected to +VOO.
16 gate electrodes.
Ｐ型ＭＯＳＦＥＴ１５とＮ型ＭＯＳＦＥＴ１６のドレイ
ン電極は互いに接続され内部入力端子１００に接続され
ている。出力駆動回路２は、出力制御回路３とソース電
極を＋ＶＤＤに接続したＰ型ＭＯＳＦＥＴ１７とソース
電極を−ＶｇＢに接続したＮ型ＭＯＳＦＥＴ１８からな
り、そのドレイン電極は互いに接続され入力端子１０に
接続され、Ｐ型Ｍ ＯＳ Ｆ Ｅ Ｔ １７のゲート電
極は出力制御回路３の出力端子１０１に接続され、Ｎ型
Ｍ ＯＳ Ｆ Ｂ７１８のゲート電極は出力制御回路３
の出力端子１０２に接続されている。出力制御回路３は
制御端子１０４と内部出力端子１０３に接続したＮ。The drain electrodes of the P-type MOSFET 15 and the N-type MOSFET 16 are connected to each other and to the internal input terminal 100. The output drive circuit 2 includes an output control circuit 3, a P-type MOSFET 17 whose source electrode is connected to +VDD, and an N-type MOSFET 18 whose source electrode is connected to -VgB, whose drain electrodes are connected to each other and to the input terminal 10, The gate electrode of the P-type MOSFET 17 is connected to the output terminal 101 of the output control circuit 3, and the gate electrode of the N-type MOSFET B718 is connected to the output control circuit 3.
is connected to the output terminal 102 of. The output control circuit 3 has an N terminal connected to the control terminal 104 and the internal output terminal 103.
Ｒ素子２０と、前記制御端子１０４に接続したインバー
タ素子２１と、前記内部出力端子１０３と前記インバー
タ素子２１の出力に接続したＮＡＮＤ素子１９とから構
成され、前記制御端子１０４及び前記内部出力端子１０
３はプルアップ素子２２に接続され常に十Ｖ。ｐ固定と
なっている。It is composed of an R element 20, an inverter element 21 connected to the control terminal 104, and a NAND element 19 connected to the internal output terminal 103 and the output of the inverter element 21.
3 is connected to the pull-up element 22 and is always at 10V. p is fixed.
入力端子１０に大雑音の入力された場合、出力駆動回路
２の制御端子１０４及び内部出力端子１０３は＋ｖＤＤ
固定となるため、Ｐ型ＭＯ３Ｆ’ＥＴ１７、Ｎ型ＭＯＳ
ＦＥＴ１８はオフし、ダイオードを構成する。これが保
護ダイオードとなるためより多くのｆａ音を吸収するこ
とができる６以上の様子を示したのが第２図の波型であ
る。When a large noise is input to the input terminal 10, the control terminal 104 and internal output terminal 103 of the output drive circuit 2 will be +vDD.
Since it is fixed, P type MO3F'ET17, N type MOS
FET 18 is turned off and forms a diode. The waveform in FIG. 2 shows the state of 6 or more where this acts as a protection diode and can absorb more fa sound.
以上の実施例はあくまでも一実施例でしかなく、前記実
施例の入力端子１０と入力駆動口′路１の間に抵抗を接
続した場合でも同様な効果を得ることができ、また、出
力制御回路を変更することで出力制御端子及び内部出力
端子を−ＶＳＳに固定して使用することも可能である。The above embodiment is just one example, and even if a resistor is connected between the input terminal 10 and the input drive port path 1 of the previous embodiment, the same effect can be obtained, and the output control circuit By changing , it is also possible to use the output control terminal and the internal output terminal fixed at -VSS.
以上のような実施例において入力信号の雑音をより小さ
くできる。In the embodiments described above, the noise of the input signal can be further reduced.
本発明は以上説明したように、入力駆動回路に入出力駆
動回路の出力駆動回路の制御信号と内部出力信号を＋ｖ
ＤＤまたは−ｖｓｓに固定したものを使用することによ
り入力信号の雑音をより小さくする入力駆動回路とする
効果がある。As explained above, the present invention provides a control signal and an internal output signal of the output drive circuit of the input drive circuit and the input/output drive circuit.
By using one fixed to DD or -vss, there is an effect that the input drive circuit can further reduce the noise of the input signal.
第１図は実施例を示す回路図、第２図は第１図の動作を
示す波型図、第３図は従来の入力駆動回路の回路図、第
４図は第３図の動作を示す波型図。
１．４・・・・・・・・・・入力駆動回路２・・・・・
・・・・・・・出力駆動回路３・・・・・・・・・・・
・出力制御回路１０．３０・・・・・・・・入力端子
１１．１２．３１．３２・・保護ダイオード１３、１５
、１７．３３．３５
・・・Ｐ型ＭＯＳＦＥＴ
１４、１６、１８．３４．３６
・・・Ｎ型Ｍ ＯＳ Ｆ Ｅ Ｔ
１９・・・・・・・・・・・ＮＡＮＤ素子２０・・・・
・・・・・・・ＮＯＲ素子２１・・・・・・・・・・・
インバータ素子２２・・・・・・・・・・・プルアップ
素子１００．３００・・・・・・内部入力端子１０１．
１０２・・・・・・出力端子
１０３・・・・・・・・・・内部出力端子１０４・・・
・・・・・・・制御端子
以上
絶１０
第２ 口
第 ３ 巳
括 ４凪Fig. 1 is a circuit diagram showing an embodiment, Fig. 2 is a waveform diagram showing the operation of Fig. 1, Fig. 3 is a circuit diagram of a conventional input drive circuit, and Fig. 4 shows the operation of Fig. 3. Waveform diagram. 1.4... Input drive circuit 2...
・・・・・・Output drive circuit 3・・・・・・・・・・・・
・Output control circuit 10.30...Input terminal 11.12.31.32...Protection diode 13, 15
, 17.33.35...P-type MOSFET 14, 16, 18.34.36...N-type MOSFET 19...NAND element 20...
......NOR element 21...
Inverter element 22...Pull-up element 100.300...Internal input terminal 101.
102... Output terminal 103... Internal output terminal 104...
・・・・・・Control terminal or more 10 2nd mouth 3rd connection 4 calm
Claims (1)
ＯＳＦＥＴと略す）を用いた半導体集積回路において、 ｂ）正極の電源端子にソース電極を接続したＰ型ＭＯＳ
ＦＥＴと、負極の電源端子にソース電極を接続したＮ型
ＭＯＳＦＥＴを少なくとも具備し、ｃ）Ｐ型ＭＯＳＦＥ
ＴとＮ型ＭＯＳＦＥＴのそれぞれのドレイン電極を互い
に接続し、前記Ｐ型ＭＯＳＦＥＴと前記Ｎ型ＭＯＳＦＥ
Ｔのそれぞれのゲート電極を互いに接続した第１の駆動
回路を少なくとも具備した入力駆動回路と ｄ）Ｐ型ＭＯＳＦＥＴとＮ型ＭＯＳＦＥＴのそれぞれの
ドレイン電極を互いに接続し、前記Ｐ型ＭＯＳＦＥＴと
前記Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極を互いに
接続した第２の駆動回路と出力制御回路からなる出力駆
動回路を使用し、ｅ）前記入力駆動回路と前記出力駆動
回路で構成された入出力駆動回路の出力駆動回路の出力
制御端子及び内部出力端子を＋Ｖ＿Ｄ＿Ｄまたは−Ｖ＿
Ｓ＿Ｓに固定することを特徴とする雑音減少型入力駆動
回路。(1)a) Insulated gate field effect transistor (hereinafter M
b) P-type MOS whose source electrode is connected to the positive power supply terminal
FET, and at least an N-type MOSFET whose source electrode is connected to a negative power supply terminal, and c) a P-type MOSFET.
The respective drain electrodes of the T-type and N-type MOSFETs are connected to each other, and the drain electrodes of the P-type MOSFET and the N-type MOSFET are connected to each other.
d) an input drive circuit comprising at least a first drive circuit in which respective gate electrodes of T are connected to each other; and d) respective drain electrodes of a P-type MOSFET and an N-type MOSFET are connected to each other; an output drive circuit consisting of a second drive circuit and an output control circuit in which respective gate electrodes of MOSFETs are connected to each other; e) output drive of an input/output drive circuit constituted by the input drive circuit and the output drive circuit; Connect the output control terminal and internal output terminal of the circuit to +V_D_D or -V_
A noise reduction type input drive circuit characterized in that the input drive circuit is fixed to S_S.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63005917A JPH01181320A (en) | 1988-01-14 | 1988-01-14 | Noise reduction type input drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63005917A JPH01181320A (en) | 1988-01-14 | 1988-01-14 | Noise reduction type input drive circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01181320A true JPH01181320A (en) | 1989-07-19 |
Family
ID=11624248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63005917A Pending JPH01181320A (en) | 1988-01-14 | 1988-01-14 | Noise reduction type input drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01181320A (en) |
-
1988
- 1988-01-14 JP JP63005917A patent/JPH01181320A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2616142B2 (en) | Output circuit | |
| JPH05243940A (en) | Output buffer device | |
| JPH0435224A (en) | Semiconductor device | |
| JPH03132115A (en) | Semiconductor integrated circuit | |
| JPH01181320A (en) | Noise reduction type input drive circuit | |
| JP2646786B2 (en) | Semiconductor output circuit | |
| JPS62135013A (en) | Output circuit | |
| JPH0677805A (en) | Output buffer circuit | |
| JPS62154915A (en) | Semiconductor integrated circuit device | |
| JPS59200524A (en) | Cmos multiplexer | |
| JP2595074B2 (en) | Semiconductor integrated circuit device | |
| JPH01246861A (en) | Semiconductor device | |
| JPS62222713A (en) | Cmos inverter circuit for delay | |
| JPH04373310A (en) | Output buffer circuit | |
| JPH08274606A (en) | Output buffer circuit | |
| KR960003220B1 (en) | Multi-input nand circuit | |
| JPH04104515A (en) | Output circuit | |
| JPH0750562A (en) | Semiconductor integrated circuit device | |
| JPH1064265A (en) | Output circuit of semiconductor device | |
| JPH04144420A (en) | Cmos/ttl conversion circuit | |
| JPH06140911A (en) | Tri-state buffer | |
| JPH04290007A (en) | Semiconductor integrated circuit device | |
| JPH0396117A (en) | Semiconductor device | |
| JPH0595265A (en) | Semiconductor device | |
| JPH02124634A (en) | Four level output circuit |