JPH0636574A - Output buffer circuit for semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a delay in a data output speed at the time of operation at low source voltage. CONSTITUTION:In addition to a regular output drive circuit 2a in an output buffer circuit in a semiconductor device, this circuit is provided with an auxiliary output drive circuit 2b, and the auxiliary output drive circuit 2b is activated only at the time of operation at low source voltage according to the output of a source voltage judgment circuit 8a. Thus, the delay in the data output speed at the time of operation at low source voltage is reduced without the problem of an output noise anxious at the time of operation at high voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a semiconductor device, and more particularly to an output buffer circuit which does not delay the output speed of data at a low power supply voltage.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing details of an output buffer circuit 1 of a conventional semiconductor device. In FIG. 4, the conventional output buffer circuit 1 is a NAN that receives an output signal a of the sense amplifier 6 and an output signal b of the output control circuit 7.
The D circuit 4 and the NOR circuit 5 which receives the output signal a of the sense amplifier 6 and the inverted value of the output signal b of the output control circuit 7 as inputs
And an output drive circuit 2a and an output terminal 3.

More specifically, the output drive circuit 2a
Is a P-channel MOS transistor Q1 whose source is connected to the power supply voltage Vcc, whose drain is connected to the output terminal 3, and whose gate is connected to the output of the NAND circuit 4, and whose source is connected to the ground potential and whose drain is output. It is composed of an n-channel MOS transistor Q2 connected to the terminal 3 and having a gate connected to the output of the NOR circuit 5.
As shown by the broken line in FIG. 1, the output terminal 3 taken out from the connection point of both the MOS transistors Q1 and Q2 of the output drive circuit 2a has a large output capacitance including the wiring capacitance of the substrate and the input capacitance of other devices. 20 will be connected. Therefore, P channel MOS transistor Q1 and n channel MOS transistor Q2 must drive such a large output capacitance 20 at high speed, and the transconductance of these MOS transistors Q1 and Q2 is set to be very large.

Next, the operation will be described. First, when the output b of the output control circuit 7 is "L" level, the output c of the NAND circuit 4 is "H" level and the output d of the NOR circuit 5 is "L" regardless of the output a of the sense amplifier 6. Since it is determined to be "level," the P-channel MOS transistor Q
Both the 1- and n-channel MOS transistors Q2 are turned off, and the output terminal 3 is in a high impedance state. Next, consider a case where the output b of the output control circuit 7 is at "H" level. In this case, the output c of the NAND circuit 4
And the output d of the NOR circuit 5 becomes "L" level if the output a of the sense amplifier 6 is "H" level, and becomes "H" level if the output a of the sense amplifier 6 is "L" level. The "level" or "L" level will be output.

Since a large output capacitance is connected to the output terminal 3 as described above, when the power supply voltage drops, the driving capability of the P-channel MOS transistor Q1 and the N-channel MOS transistor Q2 of the output drive circuit 2a. Is greatly reduced, and the data output speed is significantly delayed.

[0006]

The output buffer circuit of the conventional semiconductor device is configured as described above, and since a large capacitance is connected to the output terminal, the output drive circuit has a very large transconductance. Although it is composed of transistors, if this mutual conductance is carelessly large, output noise may become a problem. On the other hand, when the semiconductor device is operated with a low power supply voltage, the transconductance of the output drive circuit decreases in inverse proportion to the square of the voltage, which causes a problem that the output speed is significantly delayed.

The present invention has been made in order to solve the above-mentioned problems, and does not cause a problem of output noise which may occur when operating at a high power supply voltage, and outputs data at a low power supply voltage. It is an object of the present invention to provide an output buffer circuit of a semiconductor device capable of reducing the delay of the above.

[0008]

An output buffer circuit of a semiconductor device according to the present invention has an auxiliary output drive circuit in addition to a normal output drive circuit, and provides an output of a power supply voltage determination circuit for determining the level of a power supply voltage. Accordingly, the auxiliary output drive circuit is activated only when the semiconductor device is operated with a low power supply voltage.

[0009]

The auxiliary output drive circuit according to the present invention is inactive during the operation of the high power supply voltage, but is activated during the operation of the low power supply voltage. Therefore, the delay of the data output speed during the operation of the low power supply voltage can be reduced. You can

[0010]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 shows an output buffer circuit of a semiconductor device according to an embodiment of the present invention. In the figure, 8a is a power supply voltage determination circuit, 2b is provided in parallel with an output drive circuit 2a, and the output of the power supply voltage determination circuit 8a is shown. The auxiliary output drive circuit is activated or inactivated by the signal fa.

The structure of the power supply voltage determination circuit 8a will be described. 9-1a and 9-1b are n-channel load transistors connected in series in one or more stages, and 10a is two transistors 10b and 10c which form an inverter.
A P-channel MOS transistor 10d inserted between the inverter and the power supply voltage, and a transistor 10e connected between the output of the inverter and the ground.
-1b potential and chip select signal /
NOR circuit having CS and 11a as NOR circuits 1
It is an inverting circuit that receives the output of 0a.

Next, the structure of the auxiliary output drive circuit 2b will be described. 13a is an inverting circuit for obtaining an inverted signal of the output fa of the power supply voltage determination circuit 8a, and 12a and 12b are outputs fa of the power supply voltage determination circuit 8a. A CMOS transfer gate Q3 which receives the output of the inverting circuit 13a and the output of the inverting circuit 13a, respectively.
Is a P-channel MOS transistor whose source is connected to the power supply voltage Vcc, whose drain is connected to the output terminal 3 and whose gate is connected to the output c of the NAND circuit 4 through the CMOS transfer gate 12a. Q4 has its source at the ground potential. Connected, the drain is connected to the output terminal 3, and the gate is NOR via the CMOS transfer gate 12b.
An n-channel MOS transistor connected to the output d of the circuit 5, Q5 uses the output of the inverting circuit 13a as a gate input,
A P-channel MOS transistor provided between the power supply potential Vcc and the gate of the P-channel MOS transistor Q3, Q6 receives the output fa of the power-supply voltage determination circuit 8a as a gate input, and receives the ground voltage and the n-channel MOS transistor Q4.
Is an n-channel MOS transistor provided between the gate and the gate.

Next, the operation will be described. First, the operation of the power supply voltage determination circuit 8a will be described. First, consider the case where the chip select signal / CS = "L". NOR circuit 1
The threshold value of 0a fluctuates in proportion to the power supply voltage depending on the level of the power supply voltage, while the voltage obtained from the power supply voltage Vcc through the n-channel load transistors 9-1a and 9-1b is the n-channel power supply voltage. Load transistor 9-
The value changes by a constant level corresponding to the threshold values of 1a and 9-1b. Therefore, the output of the NOR circuit 10a is at "L" level when the power supply voltage is higher than a certain level.
When it is low, the "H" level is output. That is, the output fa of the power supply voltage determination circuit 8a is at "H" level during high power supply voltage operation and at "L" level during low power supply voltage operation. Considering the case where the chip select signal / CS = “H”, the output of the NOR circuit 10a is “L” level regardless of the level of the power supply voltage, and the output fa of the power supply voltage determination circuit 8a is “H”. The level is fixed.

Next, the operation of the auxiliary output drive circuit 2b will be described. First, consider the case of high power supply voltage operation, that is, the case where the output fa of the power supply voltage determination circuit 8a is "H". In this case, the CMOS transfer gates 12a and 12b are turned off, and the P-channel MOS transistor Q5 and the n-channel MOS transistor Q6 are both turned off.
Therefore, both the P-channel MOS transistor Q3 and the n-channel MOS transistor Q4 are turned off, that is, the auxiliary output drive circuit 2b becomes inactive.
Next, consider a case where the power supply voltage is low, that is, the output fa of the power supply voltage determination circuit 8a is "L". In this case, the CMOS transfer gates 12a and 12b are turned on, and both the P-channel MOS transistor Q5 and the n-channel MOS transistor Q6 are turned off.
Channel MOS transistor Q3 and n-channel MOS
Transistor Q4 is activated and transistor Q4
In addition to the output drive circuit 2a composed of Q1 and Q2 outputting data to the output terminal 3 according to the outputs c and d of the NAND circuit 4 and the NOR circuit 5, the auxiliary output drive circuit 2b composed of the transistors Q3 and Q4. Also outputs data to the output terminal 3 according to the outputs c and d.

As described above, in the embodiment shown in FIG. 1, the auxiliary output drive circuit 2b is activated only when the low power supply voltage is operated, and the auxiliary output drive transistor Q3 is added to the normal output drive transistors Q1 and Q2. Since the output terminal 3 is driven by Q4, the driving capability is increased and the delay of the data output speed at the time of low power supply voltage operation can be reduced.

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. In FIG. 2, the power supply voltage determination circuit
Has the same function as that of FIG. Reference numeral 2c is an auxiliary output drive circuit provided in parallel with the output drive circuit 2a in the second embodiment. This auxiliary output drive circuit 2
Explaining the configuration of c, the gates of Q3 and Q4 are directly P-channel and n-channel MOS transistors Q1 and Q2.
Is a P-channel or n-channel MOS transistor connected to the outputs of the NAND circuit 4 and the NOR circuit 5 through the gates of Q and Q7, respectively.
a is the gate input, power supply potential Vcc and P channel MOS
P-channel MOS provided between transistor Q3
The transistor Q8 uses the inverted signal of the output fa of the power supply voltage determination circuit 8 as a gate input and is connected to the ground potential and the n-channel MO.
N-channel MO provided between the S-transistor Q4
It is an S transistor.

Next, the operation of the second embodiment will be described. First, consider the case of high power supply voltage operation, that is, the case where the output fa of the power supply voltage determination circuit 8 is "H". In this case, P
Channel MOS transistor Q7 and n-channel MOS
Since all the transistors Q8 are turned off, the auxiliary output drive circuit 2c becomes inactive. Next, considering a low power supply voltage operation, that is, a case where the output fa of the power supply voltage determination circuit 8 is “L”, since both the P-channel MOS transistor Q7 and the n-channel MOS transistor Q8 are turned on, P
Channel MOS transistor Q3 and n-channel MOS
The transistor Q4 is activated, and in addition to the operation of the output drive circuit 2, the auxiliary output drive circuit 2c outputs data to the output terminal 3 according to the output c of the NAND circuit 4 and the output d of the NOR circuit 5. Become.

As described above, also in the second embodiment shown in FIG. 2, similarly to the first embodiment, the auxiliary output drive circuit 2c is activated in addition to the output drive circuit 2a only during the operation of the low power supply voltage. The effect of reducing the delay in the data output speed when operating at a low power supply voltage is obtained.

Example 3. Next, a third embodiment of the present invention will be described with reference to the drawings. In FIG. 3, 8a is a first power supply voltage determination circuit having the same configuration as shown in FIG.
Is a second power supply voltage determination circuit having a threshold value different from that of 8a because there is only one FET 9-1b between the power supply voltage and the input of the NOR circuit 10b. That is, when the power supply voltage Vcc is gradually decreased, first, the power supply voltage determination circuit 8 having the two FETs 9-1a and 9-2a is provided.
When the output fa of "a" first changes from "H" to "L" and further lowers the power supply voltage Vcc, one FET 9-1b
The output fb of the power supply voltage determination circuit 8b having only the output changes from "H" to "L".

Further, in FIG. 3, reference numerals 2c and 2d denote first and second auxiliary output drive circuits, which are the output fa of the first power supply voltage determination circuit 8a and the second power supply voltage determination circuit 8b, respectively.
The output fa is output to be activated or deactivated.

In the third embodiment, the operation of each circuit is the same as in the first and second embodiments. That is, in the third embodiment, both the auxiliary output drive circuits 2c and 2d are in the inactive state during the high power supply voltage operation, and P
Channel MOS transistor Q1 or n-channel MOS
The output terminal 3 is driven only by the transistor Q2. However, when operating at a low power supply voltage, only the first auxiliary output drive circuit 2c or the first auxiliary output drive circuit 2c is operated depending on the height of the power supply voltage.
The second auxiliary output drive circuits 2c and 2d are activated, and the output terminal 3 is connected to the plurality of P-channel MOS transistors Q1,
It is driven by Q3, and further Q9, and a plurality of n-channel MOS transistors Q2, Q4, and further Q10. Therefore, in this embodiment, it is possible to obtain the effect that the output drive capability is increased according to the level of the power supply voltage and the delay of the output from the output terminal can be reduced.

[0022]

As described above, according to the present invention, the auxiliary output drive circuit is provided in addition to the normal output drive circuit in the output buffer circuit of the semiconductor device, and the low power supply is provided according to the output of the power supply voltage determination circuit. Since this auxiliary output drive circuit is activated only during voltage operation, the delay in data output speed during low power supply voltage operation is reduced without causing output noise that may be a concern during high power supply voltage operation. There is an effect that an output buffer circuit of a semiconductor device capable of being obtained is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer circuit of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an output buffer circuit of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an output buffer circuit of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of an output buffer circuit of a conventional semiconductor device.

[Explanation of symbols]

 1 output buffer circuit 2a output drive circuit 2b, 2c auxiliary output drive circuit 3 output terminal 6 sense amplifier 7 output control circuit 8, 8a, 8b power supply voltage determination circuit

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 B 8941-5J

Claims (2)

[Claims] 1. An output buffer circuit of a semiconductor device, which outputs an output signal which is either a first level of a high potential or a second level of a low potential in response to a logic signal supplied from the semiconductor device. Connected between the high-potential first power supply and the output terminal,
The semiconductor device is connected between a first conductivity type first semiconductor switching element having a logic signal supplied from the semiconductor device as a gate input, the low-potential second power supply, and the output terminal. An output drive unit including a second semiconductor switching element of a second conductivity type that receives a supplied logic signal as a gate input; and a level of the power supply voltage, and determines a high potential first level or a low potential second level. Of the power supply voltage determining circuit for supplying any of the levels, and the output driving means is provided in parallel with the output of the power supply voltage determining circuit as an input, and is inactive during high power supply voltage operation and active during low power supply voltage operation. And an output buffer circuit for a semiconductor device. 2. A plurality of power supply voltage determination circuits having different threshold values, which determine a power supply voltage level and output either a high voltage first level or a low potential second level, The semiconductor device is characterized in that the outputs of the power supply voltage determination circuits having different thresholds are input, and the power supply voltage determination circuits are provided in parallel with the output drive means and the same number of auxiliary output drive means are provided. Output buffer circuit.