JPH0191268U - - Google Patents
Info
- Publication number
- JPH0191268U JPH0191268U JP18728887U JP18728887U JPH0191268U JP H0191268 U JPH0191268 U JP H0191268U JP 18728887 U JP18728887 U JP 18728887U JP 18728887 U JP18728887 U JP 18728887U JP H0191268 U JPH0191268 U JP H0191268U
- Authority
- JP
- Japan
- Prior art keywords
- plate
- circuit board
- printed circuit
- electronic component
- under test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 claims description 3
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の原理断面図、第２図は本考案
による一実施例の説明図で、ａは側面断面図、ｂ
は要部拡大図、第３図は従来の説明図で、ａは側
面断面図、ｂは要部拡大図を示す。
図において、１はプレート、２はプローブピン
、３は被試験プリント基板、４は電子部品、５は
ガイドピン、２Ａは先端、３Ａはフツトプリント
、３Ｂはビア、３Ｃは貫通穴、４Ａはリード端子
を示す。
Fig. 1 is a sectional view of the principle of the present invention, Fig. 2 is an explanatory view of an embodiment of the invention, a is a side sectional view, and b
is an enlarged view of the main part, FIG. 3 is a conventional explanatory view, a is a side sectional view, and b is an enlarged view of the main part. In the figure, 1 is a plate, 2 is a probe pin, 3 is a printed circuit board under test, 4 is an electronic component, 5 is a guide pin, 2A is a tip, 3A is a footprint, 3B is a via, 3C is a through hole, 4A is a lead Indicates terminal.
Claims (1)
４Ａが固着されることで該電子部品４の実装が行
われた被試験プリント基板３と、複数のプローブ
ピン２が所定面に突出されるように配列されたプ
レート１とを備え、該被試験プリント基板３を該
プレート１に対向させて昇降させ、該リード端子
４Ａの固着部に該プローブピン２の先端２Ａが圧
接されるフイクスチヤの構造において、 前記昇降に際して、前記被試験プリント基板３
に形成されるビア３Ｂの貫通穴３Ｃに挿入される
よう前記プレート１から突出するガイドピン５が
該プレート１に設けられて成ることを特徴とする
フイクスチヤの構造。[Claims for Utility Model Registration] A printed circuit board 3 under test on which the electronic component 4 is mounted by fixing the lead terminal 4A of the electronic component 4 to the foot print 3A, and a plurality of probe pins 2 on a predetermined surface. The printed circuit board 3 to be tested is raised and lowered facing the plate 1, and the tips 2A of the probe pins 2 are pressed into contact with the fixed portions of the lead terminals 4A. In the structure of the fixture, during the lifting and lowering, the printed circuit board under test 3
A fixture structure characterized in that the plate 1 is provided with a guide pin 5 that projects from the plate 1 so as to be inserted into the through hole 3C of the via 3B formed in the plate 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18728887U JPH0191268U (en) | 1987-12-09 | 1987-12-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18728887U JPH0191268U (en) | 1987-12-09 | 1987-12-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0191268U true JPH0191268U (en) | 1989-06-15 |
Family
ID=31478452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18728887U Pending JPH0191268U (en) | 1987-12-09 | 1987-12-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0191268U (en) |
-
1987
- 1987-12-09 JP JP18728887U patent/JPH0191268U/ja active Pending
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