JPH0184452U - - Google Patents

Info

Publication number
JPH0184452U
JPH0184452U JP18156787U JP18156787U JPH0184452U JP H0184452 U JPH0184452 U JP H0184452U JP 18156787 U JP18156787 U JP 18156787U JP 18156787 U JP18156787 U JP 18156787U JP H0184452 U JPH0184452 U JP H0184452U
Authority
JP
Japan
Prior art keywords
semiconductor element
electrode
insulating film
window
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18156787U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18156787U priority Critical patent/JPH0184452U/ja
Publication of JPH0184452U publication Critical patent/JPH0184452U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係る半導体装置の一実施例を
示す断面図、第２図は第１図の平面図、第３図は
第１図の要部拡大断面図である。第４図は従来の
半導体装置の基本構造例を示す断面図、第５図は
第４図の要部拡大断面図である。 １……半導体基板、７……半導体素子、９……
電極の高電位部位、１０……電極の低電位部位、
１６……絶縁膜、１７……導電材。

Claims (1)

  1. 【実用新案登録請求の範囲】 半導体基板上に不純物を選択的に拡散して半導
    体素子を形成し、この半導体素子表面に絶縁膜を
    被着してその所定部位を窓明けし、その窓明け部
    位に電極及び配線パターンを被着したものにおい
    て、 上記電極及び配線パターンの高電位部位と低電
    位部位間の絶縁膜を導電材で分断したことを特徴
    とする半導体装置。
JP18156787U 1987-11-27 1987-11-27 Pending JPH0184452U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18156787U JPH0184452U (ja) 1987-11-27 1987-11-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18156787U JPH0184452U (ja) 1987-11-27 1987-11-27

Publications (1)

Publication Number Publication Date
JPH0184452U true JPH0184452U (ja) 1989-06-05

Family

ID=31473048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18156787U Pending JPH0184452U (ja) 1987-11-27 1987-11-27

Country Status (1)

Country Link
JP (1) JPH0184452U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57164564A (en) * 1981-04-03 1982-10-09 Nec Corp Planar semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57164564A (en) * 1981-04-03 1982-10-09 Nec Corp Planar semiconductor device

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