JPS6429826U - - Google Patents
Info
- Publication number
- JPS6429826U JPS6429826U JP12315787U JP12315787U JPS6429826U JP S6429826 U JPS6429826 U JP S6429826U JP 12315787 U JP12315787 U JP 12315787U JP 12315787 U JP12315787 U JP 12315787U JP S6429826 U JPS6429826 U JP S6429826U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- semiconductor chip
- semiconductor device
- void
- impaired
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000001771 impaired effect Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 239000011800 void material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Structure Of Printed Boards (AREA)
- Die Bonding (AREA)
Description
第1図は本考案の構成を示す図、第2図は本考
案に係る配線パターン構造を適用した半導体装置
の一例を示す図、第3図は第2図における第2層
配線パターンの平面図、第4図は半導体装置とし
ての密着型イメージセンサの製造工程を示す図で
ある。 〔符号の説明〕、1……半導体チツプ、2……
配線パターン、3……空孔、10,20……セラ
ミツクス基板、11a,21a〜21d……第1
層配線パターン、12,22……絶縁層、13,
23……第2層配線パータン、14,24……グ
レースパターン、15,25……コンタクトホー
ル、16a,26……クロム電極パターン、17
,27……光電変換膜、18a,28……透明電
極。
案に係る配線パターン構造を適用した半導体装置
の一例を示す図、第3図は第2図における第2層
配線パターンの平面図、第4図は半導体装置とし
ての密着型イメージセンサの製造工程を示す図で
ある。 〔符号の説明〕、1……半導体チツプ、2……
配線パターン、3……空孔、10,20……セラ
ミツクス基板、11a,21a〜21d……第1
層配線パターン、12,22……絶縁層、13,
23……第2層配線パータン、14,24……グ
レースパターン、15,25……コンタクトホー
ル、16a,26……クロム電極パターン、17
,27……光電変換膜、18a,28……透明電
極。
Claims (1)
- 【実用新案登録請求の範囲】 導電性金属により形成され、半導体チツプ1が
ボンデイングされるべき配線パターン2の構造で
あつて、 当該配線パターン2に半導体チツプに対する電
気的特性を損わない範囲で空孔3を形成したこと
を特徴とする半導体装置における配線パターン構
造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12315787U JPS6429826U (ja) | 1987-08-13 | 1987-08-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12315787U JPS6429826U (ja) | 1987-08-13 | 1987-08-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6429826U true JPS6429826U (ja) | 1989-02-22 |
Family
ID=31371751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12315787U Pending JPS6429826U (ja) | 1987-08-13 | 1987-08-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6429826U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63106069U (ja) * | 1986-12-27 | 1988-07-08 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58153339A (ja) * | 1982-03-05 | 1983-09-12 | Mitsubishi Electric Corp | 混成集積回路体の製造方法 |
JPS61295656A (ja) * | 1985-06-25 | 1986-12-26 | Toshiba Corp | イメ−ジセンサ |
-
1987
- 1987-08-13 JP JP12315787U patent/JPS6429826U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58153339A (ja) * | 1982-03-05 | 1983-09-12 | Mitsubishi Electric Corp | 混成集積回路体の製造方法 |
JPS61295656A (ja) * | 1985-06-25 | 1986-12-26 | Toshiba Corp | イメ−ジセンサ |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63106069U (ja) * | 1986-12-27 | 1988-07-08 |