JPH0178100U - - Google Patents
Info
- Publication number
- JPH0178100U JPH0178100U JP1987173110U JP17311087U JPH0178100U JP H0178100 U JPH0178100 U JP H0178100U JP 1987173110 U JP1987173110 U JP 1987173110U JP 17311087 U JP17311087 U JP 17311087U JP H0178100 U JPH0178100 U JP H0178100U
- Authority
- JP
- Japan
- Prior art keywords
- shield pattern
- insulating substrates
- ground terminal
- pair
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
第1図は本考案の一実施例による両面実装型混
成集積回路の説明図、第2図は従来の両面実装型
混成集積回路の模式図、第3図はシールドパター
ンを具えた従来の両面実装型混成集積回路の模式
図、である。
図中において、3,4は回路素子、5aは入出
力端子、5bはアース端子、8,9は絶縁基板、
8bは切り欠き、10はシールドパターン、10
aはシールドパターンの一部分(表呈部)、11
は混成集積回路、を示す。
Fig. 1 is an explanatory diagram of a double-sided mounting type hybrid integrated circuit according to an embodiment of the present invention, Fig. 2 is a schematic diagram of a conventional double-sided mounting type hybrid integrated circuit, and Fig. 3 is a conventional double-sided mounting type hybrid integrated circuit with a shield pattern. 1 is a schematic diagram of a type hybrid integrated circuit. In the figure, 3 and 4 are circuit elements, 5a is an input/output terminal, 5b is a ground terminal, 8 and 9 are insulating substrates,
8b is a notch, 10 is a shield pattern, 10
a is a part of the shield pattern (exposed part), 11
indicates a hybrid integrated circuit.
Claims (1)
対の絶縁基板8,9と、一対の該絶縁基板の裏面
が接するように重ねた側端部に固着するアース端
子5bとを少なくとも具え、 一方の該絶縁基板9が裏面にシールドパターン
10を具え、 他方の該絶縁基板8が該シールドパターン10
の一部分10aを表呈させる切り欠き8bを周端
部に具え、 該シールドパターン10の表呈部10aにアー
ス端子5bを接続してなることを特徴とする混成
集積回路。[Claims for Utility Model Registration] A pair of insulating substrates 8 and 9 on which circuit elements 3 and 4 are formed and mounted, and a ground terminal fixed to the side ends of the pair of insulating substrates stacked so that their back surfaces are in contact with each other. 5b, one of the insulating substrates 9 has a shield pattern 10 on the back surface, and the other insulating substrate 8 has the shield pattern 10.
A hybrid integrated circuit characterized in that a notch 8b for exposing a portion 10a of the shield pattern 10 is provided at the peripheral end thereof, and a ground terminal 5b is connected to the exposed portion 10a of the shield pattern 10.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987173110U JPH0178100U (en) | 1987-11-12 | 1987-11-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987173110U JPH0178100U (en) | 1987-11-12 | 1987-11-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0178100U true JPH0178100U (en) | 1989-05-25 |
Family
ID=31465046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987173110U Pending JPH0178100U (en) | 1987-11-12 | 1987-11-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0178100U (en) |
-
1987
- 1987-11-12 JP JP1987173110U patent/JPH0178100U/ja active Pending
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