JPH0174636U - - Google Patents
Info
- Publication number
- JPH0174636U JPH0174636U JP1987169590U JP16959087U JPH0174636U JP H0174636 U JPH0174636 U JP H0174636U JP 1987169590 U JP1987169590 U JP 1987169590U JP 16959087 U JP16959087 U JP 16959087U JP H0174636 U JPH0174636 U JP H0174636U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- circuit
- pulse signal
- synchronization
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案に係る位相ロツク検出回路を適
用した位相同期回路の一実施例を示すブロツク図
、第２図は第１図に示した実施例における各信号
を示すタイミングチヤートである。
１……端子、２……フエーズコンパレータ、３
……カウンタ、４，６……アンプ、５……ローパ
スフイルタ、７……電圧制御発振器、８……遅延
回路、９……Ｄフリツプフロツプ、１０……イク
スクルーシブオア回路、１１，１２……リトリガ
型モノステーブルマルチバイブレータ、１３……
アンド回路、１４……抵抗、１５……コンデンサ
、１６……時定数回路。
FIG. 1 is a block diagram showing an embodiment of a phase locked circuit to which a phase lock detection circuit according to the present invention is applied, and FIG. 2 is a timing chart showing each signal in the embodiment shown in FIG. 1...Terminal, 2...Phase comparator, 3
... Counter, 4, 6 ... Amplifier, 5 ... Low pass filter, 7 ... Voltage controlled oscillator, 8 ... Delay circuit, 9 ... D flip-flop, 10 ... Exclusive OR circuit, 11, 12 ... Retrigger type monostable multivibrator, 13...
AND circuit, 14...resistor, 15...capacitor, 16...time constant circuit.
Claims (1)
信号の位相に第２のパルス信号の位相を同期させ
る位相同期回路において、 前記第２のパルス信号を所定の位相だけ遅らせ
る遅延回路と、 前記第１のパルス信号をこの遅延回路の出力に
同期して取り込むフリツプフロツプと、 このフリツプフロツプの出力が所定の時間維持
されると、位相同期状態を示す信号を出力する検
出回路と を備えたことを特徴とする位相同期回路の位相
ロツク検出回路。[Claims for Utility Model Registration] A phase synchronization circuit that inputs a first pulse signal and synchronizes the phase of a second pulse signal with the phase of the first pulse signal, a delay circuit that delays the phase by a phase; a flip-flop that captures the first pulse signal in synchronization with the output of the delay circuit; and a detection device that outputs a signal indicating a phase synchronization state when the output of the flip-flop is maintained for a predetermined time. A phase lock detection circuit for a phase synchronized circuit, characterized by comprising a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169590U JPH0174636U (en) | 1987-11-05 | 1987-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169590U JPH0174636U (en) | 1987-11-05 | 1987-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0174636U true JPH0174636U (en) | 1989-05-19 |
Family
ID=31459789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987169590U Pending JPH0174636U (en) | 1987-11-05 | 1987-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0174636U (en) |
-
1987
- 1987-11-05 JP JP1987169590U patent/JPH0174636U/ja active Pending
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