JPH02144777U - - Google Patents
Info
- Publication number
- JPH02144777U JPH02144777U JP5353789U JP5353789U JPH02144777U JP H02144777 U JPH02144777 U JP H02144777U JP 5353789 U JP5353789 U JP 5353789U JP 5353789 U JP5353789 U JP 5353789U JP H02144777 U JPH02144777 U JP H02144777U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- frequency
- input signal
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009499 grossing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
は従来のＦＶＣの一例を示す図、第３図は従来の
ＦＶＣの設定周波数と入力信号の周波数が等しい
時のタイムチヤートを示す図、第４図は従来のＦ
ＶＣの設定周波数に比べて入力信号の周波数が低
い時のタイムチヤートを示す図、第５図は従来の
ＦＶＣの設定周波数に比べて入力信号の周波数が
高い時のタイムチヤートを示す図である。
図において、１９……フリツプフロツプ、２０
……クロツク発振器、２１，２２…基準パルス発
生回路、３，４……ＮＯＲゲート、５……差動増
幅器、６……不感帯回路、７……電圧リミツタ、
８……低域周波数通過フイルタである。なお、各
図中同一符号は同一または相当部分を示す。
Fig. 1 is a diagram showing an embodiment of this invention, Fig. 2 is a diagram showing an example of a conventional FVC, and Fig. 3 is a time chart when the setting frequency of the conventional FVC and the frequency of the input signal are equal. Figure 4 shows the conventional F
FIG. 5 is a diagram showing a time chart when the frequency of the input signal is lower than the set frequency of the VC, and FIG. 5 is a diagram showing a time chart when the frequency of the input signal is higher than the set frequency of the conventional FVC. In the figure, 19...flip-flop, 20
... Clock oscillator, 21, 22 ... Reference pulse generation circuit, 3, 4 ... NOR gate, 5 ... Differential amplifier, 6 ... Dead band circuit, 7 ... Voltage limiter,
8...Low frequency pass filter. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
ル電圧が零となる周波数電圧変換器において、入
力信号とクロツクを同期させるフリツプフロツプ
と、上記フリツプフロツプの出力パルスに同期し
て、クロツクから基準のパルスを発生する論理回
路と、上記基準パルスと入力信号のパルス幅の差
を検出するＮＯＲゲートと、上記ＮＯＲゲートの
出力信号を増幅する差動増幅器と、上記差動増幅
器のオフセツトを消去する不感帯回路と、出力電
圧の最大値を決定するための電圧リミツタと、上
記電圧リミツタの出力を平滑する低域周波数通過
フイルタを備えた周波数電圧変換器。 A frequency-voltage converter that produces zero output voltage and zero ripple voltage at an arbitrarily set frequency includes a flip-flop that synchronizes the input signal and the clock, and a reference pulse generated from the clock in synchronization with the output pulse of the flip-flop. a NOR gate that detects a difference in pulse width between the reference pulse and the input signal, a differential amplifier that amplifies the output signal of the NOR gate, and a dead band circuit that eliminates the offset of the differential amplifier; A frequency-voltage converter comprising a voltage limiter for determining the maximum value of the output voltage and a low frequency pass filter for smoothing the output of the voltage limiter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5353789U JPH02144777U (en) | 1989-05-10 | 1989-05-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5353789U JPH02144777U (en) | 1989-05-10 | 1989-05-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02144777U true JPH02144777U (en) | 1990-12-07 |
Family
ID=31574808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5353789U Pending JPH02144777U (en) | 1989-05-10 | 1989-05-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02144777U (en) |
-
1989
- 1989-05-10 JP JP5353789U patent/JPH02144777U/ja active Pending
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