JPH02128433U - - Google Patents
Info
- Publication number
- JPH02128433U JPH02128433U JP3620889U JP3620889U JPH02128433U JP H02128433 U JPH02128433 U JP H02128433U JP 3620889 U JP3620889 U JP 3620889U JP 3620889 U JP3620889 U JP 3620889U JP H02128433 U JPH02128433 U JP H02128433U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- phase
- circuit
- integrator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案に係る位相同期回路の一実施例
を示す構成ブロツク図、第２図は第１図装置の動
作を示すタイムチヤート、第３図は位相同期回路
の従来例を示す構成ブロツク図、第４図は第３図
装置の動作を示すタイムチヤート、第５図は本考
案に係る位相同期回路の他の実施例を示す構成ブ
ロツク図である。
２……位相検出部、７……積分器、９……電圧
制御発振器、１１……第１のホールド回路、１２
……第２のホールド回路、１３……制御回路、１
８……バンドパスフイルタ、１９……検波器、Ｓ
Ｒ……基準周波数信号、ＨＢ……ノイズ信号の最
小値、ＨＰ……ノイズ信号の最大値。
FIG. 1 is a configuration block diagram showing one embodiment of the phase-locked circuit according to the present invention, FIG. 2 is a time chart showing the operation of the device shown in FIG. 1, and FIG. 3 is a configuration block diagram showing a conventional example of the phase-locked circuit. 4 is a time chart showing the operation of the device shown in FIG. 3, and FIG. 5 is a block diagram showing another embodiment of the phase locked circuit according to the present invention. 2... Phase detection section, 7... Integrator, 9... Voltage controlled oscillator, 11... First hold circuit, 12
...Second hold circuit, 13...Control circuit, 1
8...Band pass filter, 19...Detector, S
R...Reference frequency signal, HB...Minimum value of noise signal, HP...Maximum value of noise signal.
Claims (1)
数信号との位相差を位相検出部で検出し前記位相
検出部の出力を積分器を介して前記電圧制御発振
器の入力に帰還する位相同期回路において、基準
周波数信号と同期して積分器の出力信号に重畳す
るノイズ信号の大きさを検出する検出回路と、こ
の検出回路の出力に対応して前記積分器の入力に
前記ノイズ信号を相殺するようなオフセツト信号
およびパルス信号の少なくともいずれか一方を加
える制御回路とを備えたことを特徴とする位相同
期回路。 A phase synchronized circuit detects a phase difference between a signal based on the output of a voltage controlled oscillator and a reference frequency signal using a phase detection section, and returns the output of the phase detection section to the input of the voltage controlled oscillator via an integrator. A detection circuit that detects the magnitude of a noise signal superimposed on the output signal of the integrator in synchronization with the frequency signal, and an offset that cancels out the noise signal at the input of the integrator corresponding to the output of the detection circuit. A phase synchronized circuit comprising: a control circuit that applies at least one of a signal and a pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3620889U JPH02128433U (en) | 1989-03-29 | 1989-03-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3620889U JPH02128433U (en) | 1989-03-29 | 1989-03-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02128433U true JPH02128433U (en) | 1990-10-23 |
Family
ID=31542241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3620889U Pending JPH02128433U (en) | 1989-03-29 | 1989-03-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02128433U (en) |
-
1989
- 1989-03-29 JP JP3620889U patent/JPH02128433U/ja active Pending
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