JPH01735A - Method for forming compound semiconductor conductive layer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Application Field] The present invention relates to a method for forming a compound semiconductor conductive layer, and in particular, after implanting impurities into a compound semiconductor, the compound semiconductor is annealed to form an ion-implanted layer. This relates to a method for activating.

[Conventional technology]

In recent years, GaAS has been developed to speed up semiconductor integrated circuits.
Ga AS integrated circuits using Ga AS as conductive layers are being actively developed. In order to increase the speed of GaAs integrated circuits,
It is essential to increase the mutual conductance (gm) of field effect transistors, which are the basic elements thereof.

gm can be increased by increasing the carrier concentration in the active layer (channel layer), but the increase in the carrier concentration in the active layer also causes a shift of the threshold voltage of the field effect transistor to the negative side. That is, the absolute value increases, leading to an increase in power consumption and a decrease in operating speed. Therefore, in order to increase the absolute value of the threshold voltage and gm, it is necessary to form a thin channel layer with high carrier concentration.

Also, the source/drain regions with high carrier concentration reduce parasitic resistance and improve gm.

When forming a conductive layer (channel layer, source/drain layer, etc.) by an ion implantation method with excellent uniformity, controllability, and productivity, an annealing process is essential. In annealing, in order to prevent thermal decomposition of the constituent elements, a method is generally adopted in which a protective film is formed on the substrate surface and then annealing is performed. - As an example, a case will be described in which a conductive layer of an n-type field effect transistor is formed on a GaAs substrate. FIG. 2 is a diagram illustrating an example of the prior art, in which 9 is a GaAs substrate, 10 is a layer with a relatively small amount of implantation (hereinafter referred to as n layer) which becomes a channel layer of a field effect transistor, 11 and 14.
1 is a silicon ion to be implanted, 12 is a resist, I3 is a layer with a large amount of implantation (hereinafter referred to as an n layer) which becomes a source and drain region of a field effect transistor, and 15 is a silicon nitride film. First, as shown in Figure 81, an n-layer IO is formed by silicon ion implantation.Next, as shown in Figure b1, ion is implanted into silicon using the resist 2 as a mask to form an n layer 13. (As shown in Figure C1, after removing the resist, there is a silicon nitride film on both sides.
5 is deposited and annealed in an electric furnace to electrically activate the ion implantation layer and form a conductive layer.

After forming conductivity, is it maintained? ! ! The film is removed and a metal layer as an electrode is provided to complete the semiconductor device.

The silicon nitride film used as the protective film is excellent in terms of processing and removal, and there is no diffusion of Ga, a compound semiconductor structural element, into the film during high-temperature activation processing, so it can be used as a channel layer (n layer). However, the activation rate of the highly doped source/drain region (N1 layer) cannot be sufficiently increased, and the parasitic resistance is large. on the other hand,
Although a silicon oxide film, which is used as a protective film similar to a silicon nitride film, can achieve a high activation rate, external diffusion of gallium (Ga) occurs from the substrate during high-temperature activation treatment, and gallium vacancies near the substrate surface occur. As a result, QaAs particles are generated in large quantities through the gallium vacancy.
Since abnormal growth and diffusion of silicon occurs on the Fi side,
Not suitable for thinning channel layers.

That is, it is thought that a silicon oxide film (SiOz) easily attracts Ga because oxygen and Ga easily combine. Other films have advantages and disadvantages, and the optimal protective film for annealing has not been determined. That is, for example, aluminum nitride (AβN) has a coefficient of thermal expansion close to that of the substrate, so it causes less distortion to the crystal and is suitable for surface protection, but removing the protective film requires hot phosphoric acid, which has extremely high etching properties, and must be controlled so as not to etch the substrate. It was difficult to do so due to the process. Also, with respect to silicon nitride oxide (S i ON), it is necessary to control the film quality with high accuracy in order to highly activate the ion implantation layer, but this has been difficult to implement.

In addition, the conventional annealing method of high-temperature activation treatment of ion-implanted layers has the problem of large diffusion of implanted impurities and insufficient increase in activation rate because the high-temperature heat treatment is performed in an electric furnace to a sufficient extent. Ta. On the other hand, the short-time annealing method uses a high-output halogen lamp, arc lamp, carbon heater, etc. to electrically activate the ion-implanted layer through high-temperature treatment for a short time, and the substrate can be heated in less than 1 minute. Because of the ability to heat the process using IT, it is possible to suppress the diffusion of implanted impurities to an extremely small level compared to conventional methods, and
It has the advantage of providing a high activation rate and high carrier concentration. For example, in the case of Si implantation into Ga 8, the maximum Toyaria concentration 2X10"crrM' obtained in an electric furnace can be reduced to approximately IXIQ19cm by using lamp annealing.
-' becomes. However, in lamp annealing, the optimal temperature or optimal time for obtaining a high activation rate strongly depends on the implantation amount, and as the implantation amount increases,
Shift to the long side. When annealing regions with different implant doses (n, n-layer) at once, as in the fabrication of field effect transistors, it is not possible to fully activate all regions, and the advantages of short-time annealing cannot be fully utilized. I couldn't pull it out. That is, when the n-layer is adjusted to the optimum conditions, the activation rate of the n-layer tends to eventually decrease.

This is because As is removed from the n-layer and becomes an acceptor, which is equivalent to a decrease in the activation rate from the perspective of electrons.

[Means for solving problems]

[Object of the Invention] The object of the present invention is to eliminate the drawbacks of the prior art,
Suppressing the diffusion of both a low concentration impurity layer with a relatively small implantation amount and a high concentration impurity layer with a higher implantation amount formed in a compound semiconductor by multiple selective ion implantations in a single annealing process, and It is an object of the present invention to provide a method for forming a compound semiconductor conductive layer that can be sufficiently activated to form a thin conductive layer with high concentration necessary for improving the performance of integrated circuits with good controllability.

[Structure of the invention]

In the process of activating and annealing a low-concentration impurity layer and a high-concentration impurity layer formed by multiple ion implantations into a compound semiconductor substrate, the present invention provides a protective film that can obtain a high activation rate on the surface of the high-concentration layer. After depositing and forming a protective film on the low-concentration surface that has excellent controllability and suppressing diffusion of semiconductor constituent elements into the film and impurity diffusion, high-temperature short-time annealing for 1 minute or less is performed to remove impurities. It is characterized by forming a conductive layer by sufficiently activating the layer without diffusion.

This method differs from the conventional technology in that the high concentration impurity layer and the low concentration impurity layer are covered with separate protective films having different properties, and short-time annealing is used, which is superior in activation and reduces diffusion of impurities.

〔Example〕

The present invention will be explained below with reference to Examples. Figure 1 (al~
(e) uses a GaAs substrate as a compound semiconductor substrate, and the conductive layer (n, n layer) of an n-type field effect transistor.
1 is a diagram illustrating the present invention in the case of forming a G
An aAs substrate, 2 is an n layer, 3 and 6 are silicon ions, 4 is a resist, 5 is an n4 layer, 7 is a silicon oxide film, and 8 is a silicon nitride film.

First, as shown in the ta+ diagram, a 0 layer 2 is formed by silicon ion implantation. Next, (as shown in figure b1, resist 4
Using this as a mask, silicon ions 6 are implanted to form an n layer 5. Next, a silicon oxide film or a silicon oxynitride film 7 is deposited by a sputtering method or an electron cyclotron resonance (ECR) type plasma CVD method that can be deposited at a low temperature of about <100° C. or lower (as shown in FIG. C1). Next, (as shown in figure d1), due to lift-off, n
Part of the resist 4 and insulating film 7 on the layer is removed. Furthermore, as shown in the figure (e), a silicon nitride film 8 is deposited on both surfaces of the sample by, for example, plasma CVD, and the high temperature is maintained for a short time of 1 minute or less using a high-output halogen lamp, arc lamp, carbon heater, etc. By performing time annealing, the n-layer and the n-layer are simultaneously electrically activated.

The surface of the n layer is covered with a protective film such as a silicon nitride film, a silicon oxide film on the n° layer surface, or a silicon oxynitride film. The silicon oxide film or silicon oxide film is active because during annealing, external diffusion of Ga atoms into the protective film and abnormal accelerated diffusion of impurity (silicon), which significantly affects the threshold voltage of the semiconductor device, occur. It is not optimal as a protective film for forming an n-layer, which requires strict reproducibility and uniformity of layer thickness and activation rate. However, if these requirements are relatively loose and
As a protective film for forming the n-layer, which requires high activation,
Silicon enters the Ga vacancy created by the withdrawal of Ga from the semiconductor, forming a shallow donor level, which is very useful because a high activation rate can be obtained. On the other hand, the silicon nitride film has the function of suppressing the diffusion of Ga into the film, so the diffusion of ion-implanted silicon is small, and an extremely thin active layer can be obtained with good reproducibility and uniformity. Excellent as a protective film for layer formation. Moreover, as shown in FIG. 3, although the activation rate is inferior to that of a silicon oxide film in a high concentration layer, almost the same high activation rate can be obtained in a low concentration layer. That is, the activation rate is inferior to point A at the portion of the horizontal axis where the amount of injection is large, point B, but the activation rate is approximately the same at the portion of the horizontal axis where the amount of injection is small, point 0.

Figures 4(a) and 4(b) show the protective film (S) before and after annealing.
The amount of Ga and As 13% in iO□ and 5iN) is
These are the results of an investigation using IMS analysis. In the case of the silicon oxide film in FIG. 4(a), before annealing #;== itself)
Although there are no Ga and As atoms in the film, a large amount of Ga atoms are detected in the film after annealing. Furthermore, increasing the annealing temperature increases the amount of Ga atoms. - In the case of the silicon nitride film in Figure 4 (b), the amounts of Ga and As atoms detected in the silicon nitride film before and after annealing are within the error range, and the silicon nitride film is outside the constituent atoms of GaAS. It is thought to be suppressing the spread.

FIGS. 5(a) and 5(b) show the results of SIMS analysis of changes in the 3i atom concentration distribution before and after annealing.

In the case of the silicon oxide film shown in FIG. 5(a), when annealed at 1030° C., the peak concentration is lower than before annealing and spreads in a deeper direction. When the annealing temperature is further increased, 3i atoms undergo accelerated diffusion, resulting in a nearly rectangular concentration distribution. This is apparently caused by excess Ga vacancies generated by out-diffusion of Ga atoms.

On the other hand, in the case of the silicon nitride film shown in FIG. 5(b), no change in the Si atom concentration distribution is observed before and after annealing.

As described above, the silicon nitride film prevents the constituent atoms of GaAs from diffusing out and prevents the Si atoms, which are implanted impurities, from diffusing. Therefore, a silicon nitride film is considered to be suitable as a protective film for forming a thin n-layer with good reproducibility and uniformity.

FIG. 6 shows the relationship between sheet carrier concentration and peak temperature during annealing. In the case of silicon nitride film, the optimum temperature of the n-layer is about 900°C, but the optimum temperature of the n-layer is about 1
The temperature is 050°C. This difference has been a problem when annealing the n and n layers simultaneously. Here, when a silicon oxide film is used for the 04 layer, although the optimum temperature is at 1100° C. or higher, even when annealing at 900° C., the same value as the maximum sheet gear density can be obtained when using a silicon nitride film.

Therefore, a silicon nitride film is deposited on the n-layer surface where controllability is important, and a silicon oxide film or silicon oxynitride film is deposited on the surface of the source and drain n-layer layers where high activation rate, that is, low resistance is desired. A good conductive layer can be formed by depositing and annealing for a short time.

In addition, as the annealing protective film, as mentioned above, SiN, S
It is not necessary that each layer of iO It goes without saying that the protective film may be a composite film (multilayer structure).

〔Effect of the invention〕

As explained above, according to the present invention, a sufficient activation rate can be obtained in all regions of the compound semiconductor substrate where the implantation amount is different, and formation can be performed with good controllability.
It is possible to easily improve the electrical characteristics and controllability of elements such as transistors.

[Brief explanation of the drawing]

Figures 1(a) to (e) are cross-sectional views illustrating the formation of a W conductive layer in an n-type field effect transistor according to the present invention in the order of steps, and FIGS. The cross-sectional views shown in sequence and FIG. 3 are diagrams of experimental results showing the relationship between the implantation amount and the activation rate when lamp annealing is performed using a silicon nitride film or a silicon oxide film as the protective film according to the present invention. Figure 4 (al(b)) shows the results of SIMS analysis of the amounts of Ga and As atoms in the protective film 5iOz and SiN before and after annealing according to the present invention. SIMS shows changes in Si (silicon) atomic concentration distribution before and after annealing according to the invention.
The results of the analysis are shown below. FIG. 6 shows the relationship between the sheet carrier concentration and the peak temperature during annealing according to the Zero' invention. 1.9-GaAs substrate, 2.10-n layer, 3°6.11
．． 14... Silicon ion, 4.12... Resist, 5, 13... N layer layer, 7... Silicon oxide film, 8
．． 15...Silicon nitride film Figure 1 Figure 2 Depth from surface Figure 4 (a) Surface; Depth of 51 etc. Figure 4 (b) Depth from surface (μm) Figure 5 (a) ) Depth from the surface (Pm) Figure 5 (Procedural amendment IO, 1988, Day 1, Case description 1988 Patent Application No. 168206'29 Title of the invention Method for forming a compound semiconductor conductive layer 3 , Relationship between the amendment and the cheater case Patent applicant address 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Name (422) Nippon Telegraph and Telephone Corporation Representative Makoto Fuji
Kou 4, Agent address: 2-5-2-6, Minami-Nagasaki, Toshima-ku, Tokyo Contents of amendment: As shown in the attached sheet (11 Insert [patent application pursuant to the proviso to Article 38 of the Patent Law] in the upper right corner of the application) (2) Insert 1 line of the application below the title of the invention column, ``1', number of inventions stated in the claims 2''.

Claims (3)

[Claims] (1) In the process of forming a conductive layer by activating a low-concentration impurity layer and a high-concentration impurity layer formed by multiple ion implantations into a compound semiconductor substrate by annealing with a protective film, A protective film is deposited on the surface of the impurity layer to suppress the diffusion of impurities, and a protective film that provides a high activation rate is deposited on the surface of the highly concentrated impurity layer.After that, annealing is performed to remove the impurity layer. 1. A method for forming a compound semiconductor conductive layer, comprising the step of activating it to obtain a conductive layer. (2) A conductive layer is formed by activating an impurity layer with a relatively small amount of implantation and an impurity layer with a higher amount of implantation formed by multiple ion implantations on a compound semiconductor substrate by annealing with a protective film. In the process, a protective film is deposited on the surface of the impurity layer, which is implanted in a relatively small amount, to suppress the diffusion of impurity ions during the activation heat treatment of the compound semiconductor constituent elements into the protective film, and the impurity layer, which is implanted in a relatively small amount, is The method is characterized by comprising the steps of depositing a protective film with a high activation rate on the surface of the layer, and then performing annealing for a very short time to activate the impurity layer to obtain a conductive layer. A method for forming a compound semiconductor conductive layer. (3) A patent characterized in that gallium arsenide is used as the compound semiconductor, a silicon nitride film is deposited on the surface of the impurity layer with a relatively small amount of implantation, and a silicon oxide film or silicon oxynitride film is deposited on the surface of the high-temperature impurity layer. A method for forming a compound semiconductor conductive layer according to claim 1 or 2.