JPS64735A - Forming method of compound semiconductor conductive layer - Google Patents

Forming method of compound semiconductor conductive layer

Info

Publication number
JPS64735A
JPS64735A JP16820687A JP16820687A JPS64735A JP S64735 A JPS64735 A JP S64735A JP 16820687 A JP16820687 A JP 16820687A JP 16820687 A JP16820687 A JP 16820687A JP S64735 A JPS64735 A JP S64735A
Authority
JP
Japan
Prior art keywords
layer
silicon
film
impurity
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16820687A
Other languages
Japanese (ja)
Other versions
JPH01735A (en
JP2528660B2 (en
Inventor
Suehiro Sugitani
Kimiyoshi Yamazaki
Hajime Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62168206A priority Critical patent/JP2528660B2/en
Publication of JPH01735A publication Critical patent/JPH01735A/en
Publication of JPS64735A publication Critical patent/JPS64735A/en
Application granted granted Critical
Publication of JP2528660B2 publication Critical patent/JP2528660B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To prevent the increase of the diffusion of an implanted impurity by coating a high-concentration impurity layer and a low-concentration impurity layer with separate protective film having different properties and using annealing in a short time when activation is improved and the impurity is hardly diffused.
CONSTITUTION: An N layer 2 is formed through the implantation of silicon ions. Silicon ions 6 are implanted, using a resist 4 as a mask, thus shaping an N+ layer 5. A silicon film or a silicon oxynitride film 7 is deposited through a sputtering method capable of depositing at a low temperature of approximately 100°C or a temperature lower than 100°C or an electron cyclotron resonance type plasma CVD method. The resist 4 on the N layer and one part of an insulating film 7 are removed through lift-off. Silicon nitride films 8 are attached and shaped onto both surfaces of a sample through a method such as a plasma CVD method, and the N layer and the N+ layer are electrically activated simultaneously through short time annealing of the high-temperature holding time of 1 min or less by using a halogen lamp, etc. having a high output. The surface of the the N layer is coated with an silicon nitride and the surface of N+ layer with the protective film of the silicon oxide film or the silicon oxynitride film.
COPYRIGHT: (C)1989,JPO&Japio
JP62168206A 1987-02-06 1987-07-06 Method for forming compound semiconductor conductive layer Expired - Fee Related JP2528660B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168206A JP2528660B2 (en) 1987-02-06 1987-07-06 Method for forming compound semiconductor conductive layer

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2589887 1987-02-06
JP62-25898 1987-02-06
JP62168206A JP2528660B2 (en) 1987-02-06 1987-07-06 Method for forming compound semiconductor conductive layer

Publications (3)

Publication Number Publication Date
JPH01735A JPH01735A (en) 1989-01-05
JPS64735A true JPS64735A (en) 1989-01-05
JP2528660B2 JP2528660B2 (en) 1996-08-28

Family

ID=26363592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168206A Expired - Fee Related JP2528660B2 (en) 1987-02-06 1987-07-06 Method for forming compound semiconductor conductive layer

Country Status (1)

Country Link
JP (1) JP2528660B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496232A (en) * 1990-08-04 1992-03-27 Sumitomo Electric Ind Ltd Heat treatment method for compound semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496232A (en) * 1990-08-04 1992-03-27 Sumitomo Electric Ind Ltd Heat treatment method for compound semiconductor wafer

Also Published As

Publication number Publication date
JP2528660B2 (en) 1996-08-28

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees