RU1145838C - Method of manufacturing hf quick-acting transistor structures - Google Patents

Description

regions with G1omo (for metallization, as well as the introduction of an additional ionic impurity into the dielectric layer by implantation. However, the introduction of an impurity of the same type with the substrate into the surface layer of the semiconductor substrate and increasing its bulk end (- (traction inevitably leads to a decrease in the width of the bulk charge in a sufficiently high-resistance substrate, which serves as the collector’s body and, consequently, to decrease the breakdown voltage of the collector junction.Is goal: to achieve an increase in the breakdown voltage of the pn junctions with decreasing leakage currents The goal is achieved by the fact that in the method of manufacturing RF transistor structures, b-switching the surface of the semiconductor under the spoon with a dielectric layer, opening windows about it to sequentially form the base and emitter regions coated with a dielectric layer; areas by metallization, as well as the introduction of an additional impurity into the dielectric layer by implantation of ions. After the metallization is formed, .1 the sign of the built-in charge in the dielectric is determined skom layer and an impurity is introduced, wherein the impurity type of exposure is opposite charge in the dielectric layer, and then carried out nizkotemperatur1- first annealing. In this case, formed in the usual process of manufacturing a transistor structure and finally formed and defined built-in charge in the protective dielectric layer, for example, is positive, due to the presence in the composition of the silicon dioxide layer of an impurity having donor properties (P, As), or due to imperfection structure, causes the appearance of surface channels in the semiconductor substrate, and if there is an pn junction emerging on the surface, it bends it, which in the case of a transistor structure leads to locally to a change in the voltage of the electric field applied to the pn junction, and a decrease in its breakdown voltage, determined by the established level of leakage current. Easily controlled ion implantation introduction only into the protective dielectric layer above the places where the pn junction exits onto the surface of the impurity, which is opposite in effect to the charge sign in the added oxide or the sign of the built-in charge, compensates the built-in charge in the oxide and eliminating the possibility of surface channels, which in the case of a transistor structure reduces the curvature of the volume charge emerging on the surface of the layer, approximates the conductivity characteristics of the substrate material in the surface the rest of the layer to bulk and reduces leakage currents with an increase in the breakdown voltage of the main collector junction due to a decrease in the density of injection currents and elimination of the causes of thermal instability and secondary breakdown. In addition, the elimination of the introduction of impurity D by the region of the pn junction by ion implantation, which creates a series of bulk defects in the semiconductor material that do not disappear at an acceptable value from) 1 (yy to, helps to stabilize the electrical characteristics of the transistor structure. The sequential stages of manufacturing an RF transistor structure using the example of a KT312 transistor are shown in Fig. 3. On a semiconductor substrate 1, for example, p-type silicon with a resistivity of 0.00 Ohm-cm, an epitaxial layer of 2 birds is grown and with a resistivity of k Ohm-cm, a masking coating, for example thermal oxide, is grown at a temperature of 120 ° C in a combined mode in dry and moistened Oxygen to a thickness of 0.6 μm. In coating 3, windows A are opened through which ion doping with or by thermal diffusion form a base region of 5 P type, for example, in the first stage for 25-35 min to a surface resistance value of Rg 50 - 70 Ohm / P and in the second stage gris 115iC in a combined mode in a medium of dry and moistened acid lorod for 120 minutes to the depth of transition junction X 3,5tO, r microns and Кц 110-160 Ohm / о. At the same time, on the base region 5 simultaneously form

5.

masking coating 6 with a thickness of 0.5 0.7 μm “In coating 6, photolithography opens the windows 7 through which thermal diffusion forms an emitter region 8 of the p-type, for example, at the first stage of PC1 at lOSOC in argon atmosphere with the addition of oxygen for 15 min with the flow of the diffusant in an open pipe and 5 minute displacement of the diffusant flow to. the depths of the emitter region X. 1.1 microns and R 3 Ohm / P and in the second stage at 1050 ° C in an oxygen medium to a thickness of the base region liX j of 0.6-0.8 microns. Moreover, a protective coating 9 is simultaneously formed on the eiitter region 8 on the basis of phosphorosilicate glass (FSS) with a thickness of 0.2-0.25 microns.

Windows 10, 11 are opened in the coatings 6, 9, through which they contact with metallization 12, 13, for example, a layer of aluminum with a thickness of 1.5-2 microns. In this case, it is necessary that the metallization 13, which is a kind of mask, leave the emitter-base transition loop open, and the metallization 12 - the base-collector transition loop.

After this, heat treatment is carried out, in particular, burning aluminum to provide lower contact resistance in the contact at 510550 ° C in nitrogen for 15 min. Then, using CV measurements, the charge sign in the dielectric layer is determined on substrate satellites processed in parallel with basic substrates and structures.

In order to increase the breakdown voltage, the finished metallized transistor structures are exposed to impurity ions, which creates a charge in the most critical region of the structure’s covered coating above the exit of the pn junction to the surface.

58386

Doping of the oxide is carried out with boron ions at accelerations of 10-70 kV and a dose of 2 10 -8-10 atom / cm2. The maximum concentration of implanted atoms lies in region 1 at a depth of 0, 28 μm, which should be less than the thickness of the doped oxide. After that, heat treatment is carried out in an inert medium to activate the introduced impurity, for example, at a temperature of 15 minutes in argon.

Breakdown voltage received

5 transistor structures increase at a level of 100 V with a set leakage current of 0.5 μL by 20-25%. In this case, the gain in direct mode decreases l / by 20% by

0 level to 100 due to a decrease in the injection coefficient of the emitter-base transition in the near-surface layer, which allows controlling these structural parameters. Effect on other parameters

5 not found.

Application of the proposed method will increase the ultimate breakdown voltage of pn junctions simultaneously with the ability to control the gain of the finished transistor structures, i.e. regulate the range of products. In this case, an increase in breakdown voltages will make it possible to increase the reliability of transistor structures under the same operating conditions,

I

In addition, the application of the proposed method in the processing of pn-pj4 transistor structures with a built-in positive charge due to a decrease in the inverse surface p-type layers contributes to a 2A decrease in one of the main parameters

. HF transistor structures t ac at the {3rd resorption of minority carriers at the base.

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