JPH0157539B2 - - Google Patents
Info
- Publication number
- JPH0157539B2 JPH0157539B2 JP55182620A JP18262080A JPH0157539B2 JP H0157539 B2 JPH0157539 B2 JP H0157539B2 JP 55182620 A JP55182620 A JP 55182620A JP 18262080 A JP18262080 A JP 18262080A JP H0157539 B2 JPH0157539 B2 JP H0157539B2
- Authority
- JP
- Japan
- Prior art keywords
- received data
- frequency divider
- variable frequency
- bit
- mpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55182620A JPS57106255A (en) | 1980-12-23 | 1980-12-23 | Bit synchronizing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55182620A JPS57106255A (en) | 1980-12-23 | 1980-12-23 | Bit synchronizing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57106255A JPS57106255A (en) | 1982-07-02 |
| JPH0157539B2 true JPH0157539B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1989-12-06 |
Family
ID=16121466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55182620A Granted JPS57106255A (en) | 1980-12-23 | 1980-12-23 | Bit synchronizing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57106255A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6163127A (ja) * | 1984-09-04 | 1986-04-01 | Fujitsu Ltd | 時分割多重変換装置 |
| CA1279909C (en) * | 1986-12-15 | 1991-02-05 | Scott Marshall | Apparatus and method for synchronizing a communication system |
| JPH0666770B2 (ja) * | 1986-12-19 | 1994-08-24 | 三洋電機株式会社 | クロツク信号再生回路 |
| JPH07183881A (ja) * | 1993-12-22 | 1995-07-21 | Daiden Co Ltd | クロック再生装置 |
| JP2008187071A (ja) * | 2007-01-31 | 2008-08-14 | Nippon Seiki Co Ltd | プリント基板 |
-
1980
- 1980-12-23 JP JP55182620A patent/JPS57106255A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57106255A (en) | 1982-07-02 |