JPH0156572B2 - - Google Patents
Info
- Publication number
- JPH0156572B2 JPH0156572B2 JP57187101A JP18710182A JPH0156572B2 JP H0156572 B2 JPH0156572 B2 JP H0156572B2 JP 57187101 A JP57187101 A JP 57187101A JP 18710182 A JP18710182 A JP 18710182A JP H0156572 B2 JPH0156572 B2 JP H0156572B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- clock signal
- level
- signal
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/16—Circuits for carrying over pulses between successive decades
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
- H03K23/62—Gating or clocking signals not applied to all stages, i.e. asynchronous counters reversible
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18710182A JPS5975723A (ja) | 1982-10-25 | 1982-10-25 | プログラマブルカウンタ |
| US06/542,195 US4587665A (en) | 1982-10-15 | 1983-10-14 | Binary counter having buffer and coincidence circuits for the switched bistable stages thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18710182A JPS5975723A (ja) | 1982-10-25 | 1982-10-25 | プログラマブルカウンタ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5975723A JPS5975723A (ja) | 1984-04-28 |
| JPH0156572B2 true JPH0156572B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1989-11-30 |
Family
ID=16200118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18710182A Granted JPS5975723A (ja) | 1982-10-15 | 1982-10-25 | プログラマブルカウンタ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5975723A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4891827A (en) * | 1988-03-07 | 1990-01-02 | Digital Equipment Corporation | Loadable ripple counter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6017179B2 (ja) * | 1978-06-21 | 1985-05-01 | 三菱電機株式会社 | プリセツト回路 |
| JPS56747A (en) * | 1979-06-18 | 1981-01-07 | Toshiba Corp | Binary counter circuit |
-
1982
- 1982-10-25 JP JP18710182A patent/JPS5975723A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5975723A (ja) | 1984-04-28 |