JPH0156571B2 - - Google Patents

Info

Publication number
JPH0156571B2
JPH0156571B2 JP57181707A JP18170782A JPH0156571B2 JP H0156571 B2 JPH0156571 B2 JP H0156571B2 JP 57181707 A JP57181707 A JP 57181707A JP 18170782 A JP18170782 A JP 18170782A JP H0156571 B2 JPH0156571 B2 JP H0156571B2
Authority
JP
Japan
Prior art keywords
output
clock signal
inverter
level
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57181707A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5970320A (ja
Inventor
Hiroshi Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18170782A priority Critical patent/JPS5970320A/ja
Priority to US06/542,195 priority patent/US4587665A/en
Publication of JPS5970320A publication Critical patent/JPS5970320A/ja
Publication of JPH0156571B2 publication Critical patent/JPH0156571B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/16Circuits for carrying over pulses between successive decades
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/58Gating or clocking signals not applied to all stages, i.e. asynchronous counters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/58Gating or clocking signals not applied to all stages, i.e. asynchronous counters
    • H03K23/62Gating or clocking signals not applied to all stages, i.e. asynchronous counters reversible

Landscapes

  • Manipulation Of Pulses (AREA)
  • Shift Register Type Memory (AREA)
JP18170782A 1982-10-15 1982-10-15 バイナリ−カウンタ Granted JPS5970320A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP18170782A JPS5970320A (ja) 1982-10-15 1982-10-15 バイナリ−カウンタ
US06/542,195 US4587665A (en) 1982-10-15 1983-10-14 Binary counter having buffer and coincidence circuits for the switched bistable stages thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18170782A JPS5970320A (ja) 1982-10-15 1982-10-15 バイナリ−カウンタ

Publications (2)

Publication Number Publication Date
JPS5970320A JPS5970320A (ja) 1984-04-20
JPH0156571B2 true JPH0156571B2 (en, 2012) 1989-11-30

Family

ID=16105447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18170782A Granted JPS5970320A (ja) 1982-10-15 1982-10-15 バイナリ−カウンタ

Country Status (1)

Country Link
JP (1) JPS5970320A (en, 2012)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5267559A (en) * 1975-12-02 1977-06-04 Toshiba Corp Counter
JPS5914930B2 (ja) * 1976-04-27 1984-04-06 株式会社東芝 プログラマブルカウンタ
JPS6053929B2 (ja) * 1977-09-26 1985-11-28 株式会社東芝 プログラマブルカウンタ

Also Published As

Publication number Publication date
JPS5970320A (ja) 1984-04-20

Similar Documents

Publication Publication Date Title
US5087835A (en) Positive edge triggered synchronized pulse generator
JPH0691431B2 (ja) フリツプフロツプ回路用クロツク制御回路
US4939384A (en) Flip-flop circuit
US6573775B2 (en) Integrated circuit flip-flops that utilize master and slave latched sense amplifiers
JPS6134296B2 (en, 2012)
JPH05199080A (ja) 相補型論理回路
US4933571A (en) Synchronizing flip-flop circuit configuration
JPH10190416A (ja) フリップフロップ回路
US4114052A (en) Presettable dynamic delay flip-flop circuit
US5930322A (en) Divide-by-4/5 counter
JPH09312553A (ja) 論理回路
US5111489A (en) Frequency-dividing circuit
EP0403047B1 (en) A frequency divider circuit
US4587665A (en) Binary counter having buffer and coincidence circuits for the switched bistable stages thereof
US5175753A (en) Counter cell including a latch circuit, control circuit and a pull-up circuit
US5003201A (en) Option/sequence selection circuit with sequence selection first
JPH0156571B2 (en, 2012)
JPH05102312A (ja) 半導体集積回路
JP3565257B2 (ja) フリップフロップ回路
JPH06260902A (ja) フリップフロップ回路
JPH0156572B2 (en, 2012)
JP2656241B2 (ja) アツプダウンカウンタ回路
JP2575834B2 (ja) フリップフロップ回路
JP2564300B2 (ja) ダイナミツク型フリツプフロツプ
KR0131164B1 (ko) 주/종속 플립-플롭