JPH0154862B2 - - Google Patents
Info
- Publication number
- JPH0154862B2 JPH0154862B2 JP59166704A JP16670484A JPH0154862B2 JP H0154862 B2 JPH0154862 B2 JP H0154862B2 JP 59166704 A JP59166704 A JP 59166704A JP 16670484 A JP16670484 A JP 16670484A JP H0154862 B2 JPH0154862 B2 JP H0154862B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- lead
- frame
- substrate
- metal powder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000000843 powder Substances 0.000 claims abstract description 9
- 238000003466 welding Methods 0.000 claims abstract description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000000149 penetrating effect Effects 0.000 claims abstract 2
- 238000000605 extraction Methods 0.000 claims description 4
- 229920003002 synthetic resin Polymers 0.000 abstract description 3
- 239000000057 synthetic resin Substances 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、混成集積回路基板をフレーム下部
に固着し、基板からのリード線とフレームの外部
引出端子部とを内部で溶接接続した混成集積回路
装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a hybrid integrated circuit in which a hybrid integrated circuit board is fixed to the lower part of a frame, and lead wires from the board and external lead terminals of the frame are internally connected by welding. Regarding equipment.
従来のこの種の混成集積回路装置は、第1図に
縦断面図で示すようになつている。1は混成集積
回路基板(以下「基板」と称する)、2は合成樹
脂成形品などからなるフレームで、底部に基板1
をはめ込み接着剤3で固着している。4はフレー
ム2の側部を貫通し固着して出された外部引出端
子、5は基板1の電子回路(図示は略す)の端子
部1aにはんだ6により接合され立上つたリード
線である。外部引出端子4の内部接続部4aに、
リード線5の先端部5aをマイクロスボツト溶接
により接続している。7はフレーム2上に接着さ
れ密封するカバーである。
A conventional hybrid integrated circuit device of this type is shown in a longitudinal sectional view in FIG. 1 is a hybrid integrated circuit board (hereinafter referred to as "substrate"), 2 is a frame made of a synthetic resin molded product, etc., with the board 1 on the bottom.
Insert and secure with adhesive 3. Reference numeral 4 designates an external lead-out terminal that penetrates through the side of the frame 2 and is fixed thereto, and reference numeral 5 designates a rising lead wire that is joined to the terminal portion 1a of the electronic circuit (not shown) of the board 1 by solder 6. In the internal connection part 4a of the external extraction terminal 4,
The tips 5a of the lead wires 5 are connected by microbot welding. 7 is a cover adhered onto the frame 2 to seal it.
上記従来の混成集積回路装置は、電子回路から
のリード線5と外部引出端子4との接続点が電子
回路上に位置しており、双方をマイクロスポツト
溶接したとき、溶融金属粉が飛散し電子回路の配
線間に付着し、短絡することがあり、品質上不具
合が生じていた。 In the conventional hybrid integrated circuit device described above, the connection point between the lead wire 5 from the electronic circuit and the external extraction terminal 4 is located on the electronic circuit, and when the two are micro-spot welded, molten metal powder is scattered and the electronic It could adhere between circuit wires and cause short circuits, causing quality problems.
(発明の概要〕
この発明は、フレームから出された外部引出端
子の内部接続部の下方位置に、フレームの側部内
面から遮へい板部を内方へ延ばし、基板からのリ
ード線と外部引出端子の内部接続部とのスポツト
溶接による溶融金属粉の下方への飛散を、遮へい
板部上に受止め、下方の基板の電子回路配線への
飛散付着をなくし、短絡を防止した信頼度の高い
混成集積回路装置を提供することを目的としてい
る。(Summary of the Invention) This invention provides a shielding plate portion extending inward from the inner surface of the side of the frame at a position below the internal connection portion of the external lead-out terminal extended from the frame, and a shielding plate portion extending inward from the inner surface of the side part of the frame to connect the lead wire from the board and the external lead-out terminal. A highly reliable composite that catches the downward scattering of molten metal powder caused by spot welding with the internal connection part of the board on the shield plate, eliminates scattering and adhesion to the electronic circuit wiring of the lower board, and prevents short circuits. The purpose is to provide integrated circuit devices.
第2図及び第3図はこの発明の一実施例による
混成集積回路装置の縦断面図及び平面図であり、
1,3〜7,1a,4a,5aは上記従来装置と
同一のものである。11は合成樹脂成形品などか
らなるフレーム、11aはこのフレームの側部内
面から一体に出された遮へい板部で、外部引出端
子4の接続部4aの下方位置に突出し、下方の基
板1の電子回路配線部を覆つている。基板1から
のリード線5の先端部5aと外部引出端子4の接
続部4aとのマイクロスポツト溶接による溶融金
属粉の下方への飛散を、遮へい板部11上に受止
める。これにより、下方の基板1の電子回路配線
部に溶融金属粉が飛散付着することが防止され
る。
2 and 3 are a longitudinal sectional view and a plan view of a hybrid integrated circuit device according to an embodiment of the present invention,
1, 3 to 7, 1a, 4a, and 5a are the same as those in the conventional device. 11 is a frame made of a synthetic resin molded product, etc.; 11a is a shielding plate portion integrally protruded from the side inner surface of this frame, which protrudes below the connection portion 4a of the external lead terminal 4; Covers the circuit wiring section. The downward scattering of molten metal powder due to micro spot welding between the tip end 5a of the lead wire 5 from the substrate 1 and the connection part 4a of the external lead terminal 4 is caught on the shielding plate part 11. This prevents molten metal powder from scattering and adhering to the electronic circuit wiring portion of the substrate 1 below.
以上のように、この発明によれば、外部引出端
子の内部接続部の下方位置に、フレームの側部内
面から遮へい板部を突出して設けたので、基板か
らのリード線と外部引出端子の内部接続部との溶
接による溶融金属粉の下方への飛散が、遮へい板
部上に受止められ、下方の基板の電子回路配線へ
の飛散付着がなくなり短絡が防止され、品質が向
上される。
As described above, according to the present invention, since the shielding plate part is provided below the internal connection part of the external lead-out terminal and protrudes from the inner surface of the side part of the frame, the lead wire from the board and the inside of the external lead-out terminal are provided. The downward scattering of molten metal powder due to welding with the connection part is caught on the shield plate part, and the scattering and adhesion to the electronic circuit wiring of the lower board is eliminated, short circuits are prevented, and quality is improved.
第1図は従来の混成集積回路装置の縦断面図、
第2図及び第3図はこの発明の一実施例による混
成集積回路装置の縦断面図及び平面図である。
1……混成集積回路基板、4……外部引出端
子、4a……接続部、5……リード線、5a……
先端部、11……フレーム、11a……遮へい板
部。なお、図中同一符号は同一又は相当部分を示
す。
Figure 1 is a vertical cross-sectional view of a conventional hybrid integrated circuit device.
2 and 3 are a vertical sectional view and a plan view of a hybrid integrated circuit device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Mixed integrated circuit board, 4...External extraction terminal, 4a...Connection part, 5...Lead wire, 5a...
Tip part, 11...frame, 11a...shielding plate part. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
れて上方に延ばされた混成集積回路基板、この基
板を下部に固着し上部が開口しており、外部引出
端子が側部を貫通して出されたフレーム、及びこ
のフレームの上部側部内面から一体に内方に延ば
され、上記外部引出端子の内部接続部の下方位置
に突出し、下方の上記基板の電子回路配線部を覆
う遮へい板部を備え、上記リード線の先端部と上
記外部引出端子の内部接続部との溶接による溶融
金属粉の下方への飛散を、上記遮へい板部により
受止めたことを特徴とする混成集積回路装置。1 A hybrid integrated circuit board with lead wires connected to the terminals of the electronic circuit on the top surface and extended upwards, with this board fixed to the bottom and open at the top, with external lead-out terminals penetrating the sides. A shielding plate that integrally extends inward from the inner surface of the upper side of the extended frame, protrudes below the internal connection portion of the external lead-out terminal, and covers the electronic circuit wiring portion of the substrate below. a hybrid integrated circuit device, wherein the shielding plate portion catches downward scattering of molten metal powder due to welding between the tip of the lead wire and the internal connection portion of the external extraction terminal. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59166704A JPS6143460A (en) | 1984-08-07 | 1984-08-07 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59166704A JPS6143460A (en) | 1984-08-07 | 1984-08-07 | Hybrid integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6143460A JPS6143460A (en) | 1986-03-03 |
JPH0154862B2 true JPH0154862B2 (en) | 1989-11-21 |
Family
ID=15836208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59166704A Granted JPS6143460A (en) | 1984-08-07 | 1984-08-07 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6143460A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01295481A (en) * | 1988-05-24 | 1989-11-29 | Toshiba Corp | Lead connecting method |
JP2532665B2 (en) * | 1989-06-14 | 1996-09-11 | シーケーディ株式会社 | Reed blade position detection device in reeding machine |
JPH09137342A (en) * | 1995-11-10 | 1997-05-27 | Hashizume Kenkyusho:Kk | Method for drawing warp in reed and high-precision reed drawing-in machine therefor |
-
1984
- 1984-08-07 JP JP59166704A patent/JPS6143460A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6143460A (en) | 1986-03-03 |
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