JPS63142840A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63142840A
JPS63142840A JP61291095A JP29109586A JPS63142840A JP S63142840 A JPS63142840 A JP S63142840A JP 61291095 A JP61291095 A JP 61291095A JP 29109586 A JP29109586 A JP 29109586A JP S63142840 A JPS63142840 A JP S63142840A
Authority
JP
Japan
Prior art keywords
solder
outer lead
plating layer
copper foil
onto
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61291095A
Other languages
Japanese (ja)
Inventor
Akira Matsushita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP61291095A priority Critical patent/JPS63142840A/en
Publication of JPS63142840A publication Critical patent/JPS63142840A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

PURPOSE:To bond an outer lead positively onto a copper foil in a PC board by previously forming a plating layer onto the surface and further attaching solder onto the surface of the outer lead molded to a predetermined shape. CONSTITUTION:Solder 9 is further affixed onto the surface of a previously shaped plating layer 6 in the vicinity of the nose of an outer lead 5. Solder 9 is attached before characteristics inspection through the processors of tie-bar cutting and outer-lead molding after first plating layer 6 is formed. The previously shaped plating layer 6 is also melted partially when solder 9 is affixed, but the greater part remain on the surface of the outer lead 5. When the outer lead 5 for a semiconductor device is brought into contact with the surface of a copper foil 8 in a PC board 7 and the solder of the plating layer 6 on the surface of the outer lead 5 and solder 9 on the solder of the plating layer 6 are melted through methods such as reflow, laser irradiation, thermocompression bonding, etc., in the same manner as conventional devices, a large quantity of solder being to melt between the outer lead 5 and the copper foil 8. When solder is attached previously onto the copper foil 8 at that time, the solder is also melted and melted between the outer lead 5 and the copper foil 8.
JP61291095A 1986-12-05 1986-12-05 Semiconductor device Pending JPS63142840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61291095A JPS63142840A (en) 1986-12-05 1986-12-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61291095A JPS63142840A (en) 1986-12-05 1986-12-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63142840A true JPS63142840A (en) 1988-06-15

Family

ID=17764381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61291095A Pending JPS63142840A (en) 1986-12-05 1986-12-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63142840A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0385750A (en) * 1989-08-30 1991-04-10 Yamaha Corp Semiconductor device and its mounting method
JPH05343586A (en) * 1991-03-22 1993-12-24 Akira Kitahara Surface mounting component and manufacture thereof
KR100743231B1 (en) 2001-05-10 2007-07-27 엘지전자 주식회사 Making method of PCB

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0385750A (en) * 1989-08-30 1991-04-10 Yamaha Corp Semiconductor device and its mounting method
JPH05343586A (en) * 1991-03-22 1993-12-24 Akira Kitahara Surface mounting component and manufacture thereof
KR100743231B1 (en) 2001-05-10 2007-07-27 엘지전자 주식회사 Making method of PCB

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