JPH0151075B2 - - Google Patents

Info

Publication number
JPH0151075B2
JPH0151075B2 JP59023353A JP2335384A JPH0151075B2 JP H0151075 B2 JPH0151075 B2 JP H0151075B2 JP 59023353 A JP59023353 A JP 59023353A JP 2335384 A JP2335384 A JP 2335384A JP H0151075 B2 JPH0151075 B2 JP H0151075B2
Authority
JP
Japan
Prior art keywords
layer
thick film
conductor layer
circuit conductor
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59023353A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60167497A (ja
Inventor
Hisashi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59023353A priority Critical patent/JPS60167497A/ja
Publication of JPS60167497A publication Critical patent/JPS60167497A/ja
Publication of JPH0151075B2 publication Critical patent/JPH0151075B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP59023353A 1984-02-10 1984-02-10 多層回路基板の製造方法 Granted JPS60167497A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59023353A JPS60167497A (ja) 1984-02-10 1984-02-10 多層回路基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59023353A JPS60167497A (ja) 1984-02-10 1984-02-10 多層回路基板の製造方法

Publications (2)

Publication Number Publication Date
JPS60167497A JPS60167497A (ja) 1985-08-30
JPH0151075B2 true JPH0151075B2 (cs) 1989-11-01

Family

ID=12108210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59023353A Granted JPS60167497A (ja) 1984-02-10 1984-02-10 多層回路基板の製造方法

Country Status (1)

Country Link
JP (1) JPS60167497A (cs)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS556822A (en) * 1978-06-30 1980-01-18 Oki Electric Ind Co Ltd Method of manufacturing ceramic multiilayer wiring board
JPS5651899A (en) * 1979-10-05 1981-05-09 Nippon Electric Co Method of manufacturing high density multilayer circuit board
JPS56118395A (en) * 1980-02-23 1981-09-17 Tokyo Shibaura Electric Co Method of forming multilayer wire
JPS5817696A (ja) * 1981-07-23 1983-02-01 日立化成工業株式会社 多層印刷配線板の製造法

Also Published As

Publication number Publication date
JPS60167497A (ja) 1985-08-30

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