JPH0147011B2 - - Google Patents
Info
- Publication number
- JPH0147011B2 JPH0147011B2 JP54161964A JP16196479A JPH0147011B2 JP H0147011 B2 JPH0147011 B2 JP H0147011B2 JP 54161964 A JP54161964 A JP 54161964A JP 16196479 A JP16196479 A JP 16196479A JP H0147011 B2 JPH0147011 B2 JP H0147011B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- polycrystalline silicon
- silicon thin
- metal silicide
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000005259 measurement Methods 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 description 7
- 230000002950 deficient Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000700 radioactive tracer Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の評価方法に関し、特に多
結晶シリコン薄膜およびその上に形成された金属
シリサイドでなる配線の評価方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for evaluating a semiconductor device, and more particularly to a method for evaluating a wiring made of a polycrystalline silicon thin film and metal silicide formed thereon.
従来、半導体装置には、その製造技術上の単純
さ、便利さ、容易に可能な高集積度、等の為に多
結晶シリコン薄膜が使用されている。特に多結晶
シリコン薄膜による電極及び配線への応用は一般
化している。しかし、多結晶シリコン薄膜を配線
として利用する場合、その抵抗値が高いという欠
点を有しており、半導体装置の設計に於いて多く
の制限を受けている。その為に多結晶シリコン薄
膜表面に金属シリサイド層を形成することによ
り、その抵抗値を低下させる方法がある。 Conventionally, polycrystalline silicon thin films have been used in semiconductor devices because of their simplicity in manufacturing technology, convenience, high degree of integration, etc. In particular, the application of polycrystalline silicon thin films to electrodes and wiring has become common. However, when polycrystalline silicon thin films are used as interconnections, they have the drawback of high resistance, and are subject to many limitations in the design of semiconductor devices. For this purpose, there is a method of lowering the resistance value by forming a metal silicide layer on the surface of a polycrystalline silicon thin film.
しかるに、従来の半導体装置の製造方法では、
この金属シリサイド層を形成した多結晶シリコン
薄膜配線の層抵抗値を、パターンの微細化に伴
い、金属シリサイド層の形成直後はもとより完成
後にもその特性を測定できなかつた。金属シリサ
イド層の形成後にその出来、不出来をモニターす
ることができないため、不良品の場合でも後の工
程に進めることにより、きわめて不経済であつ
た。又、不良品の発生が直ぐに発見されないた
め、同じ条件で製造される後続のロツトも同様に
不良品になつてしまうこともあつた。更に、完成
後も配線の特性を直接モニターできないことか
ら、特に装置の不良原因が配線抵抗が大きいこと
による場合、その解析が困難であつた。 However, in conventional semiconductor device manufacturing methods,
Due to the miniaturization of patterns, it has become impossible to measure the layer resistance value of the polycrystalline silicon thin film wiring formed with this metal silicide layer, not only immediately after the metal silicide layer is formed, but also after its completion. Since it is not possible to monitor the success or failure of the metal silicide layer after it is formed, it is extremely uneconomical to proceed to a later process even in the case of a defective product. Furthermore, since the occurrence of defective products is not detected immediately, subsequent lots produced under the same conditions may also end up being defective. Furthermore, since the characteristics of the wiring cannot be directly monitored even after completion, it has been difficult to analyze the failure of the device, especially when the cause is high wiring resistance.
本発明の目的は、そのような配線の評価を容易
に行ない得る方法を提供することにある。 An object of the present invention is to provide a method that allows easy evaluation of such wiring.
本発明による方法は、それぞれが多結晶シリコ
ン薄膜とその上に形成された金属シリサイドとで
なり互いに幅が異なる少なくとも二つの素子をモ
ニタ素子として設け、各モニタ素子の抵抗値をそ
れぞれ測定し、その測定結果から配線の層抵抗の
変化と幅の変化とを評価することにある。 In the method according to the present invention, at least two elements each consisting of a polycrystalline silicon thin film and a metal silicide formed thereon and having different widths are provided as monitor elements, the resistance value of each monitor element is measured, and the resistance value of each monitor element is measured. The objective is to evaluate changes in layer resistance and width of wiring from measurement results.
以下本発明については、図面を用いて説明す
る。本発明の原理は、第１図に示す様な幅Ｗ、長
さＬのチエツク用パツドＰ，P′を有する多結晶シ
リコン薄膜パターンを、装置内の邪魔にならない
箇所に、所要配線と同時に形成した後、やはり所
要配線と同時にパターン表面に金属シリサイド層
を形成し、その後その抵抗値を測定することによ
り、多結晶シリコン薄膜配線の層抵抗を求め、所
要配線の出来、不出来をモニターすることにあ
る。層抵抗ρs（Ω／□）は、測定値をＲ（Ω）とす
れば次式で与えられる。 The present invention will be explained below using the drawings. The principle of the present invention is to simultaneously form a polycrystalline silicon thin film pattern having check pads P and P' with a width W and a length L as shown in Fig. 1 in an out-of-the-way location within the device at the same time as required wiring. After that, a metal silicide layer is formed on the pattern surface at the same time as the required wiring, and the resistance value is then measured to determine the layer resistance of the polycrystalline silicon thin film wiring and monitor the success or failure of the required wiring. It is in. The layer resistance ρs (Ω/□) is given by the following equation, where the measured value is R (Ω).
ρs＝RW／Ｌ（Ω／□）
配線抵抗は、一般に層抵抗が小さいので、幅Ｗ
と長さＬとの比Ｌ／Ｗは大きくした方がモニター
精度が良いし、又幅Ｗによつて層抵抗が異なる事
が充分考えられるので、配線幅も２種類以上用意
した方が好ましい。 ρ s = RW/L (Ω/□) Wiring resistance generally has a small layer resistance, so the width W
The monitoring accuracy is better when the ratio L/W between the width and the length L is increased, and since it is quite possible that the layer resistance differs depending on the width W, it is preferable to prepare two or more types of wiring widths.
第２図に本発明の好ましい実施例を示す。必要
な不純物拡散層や必要な絶縁膜の形成された半導
体多基板上に、例えば5000Åの厚さの多結晶シリ
コン薄膜をCVD法により形成する。次に、選択
酸化法を用いて前記多結晶シリコン薄膜をパター
ニングして、前記基板に形成された各半導体装置
の内部領域７に所要の配線を形成する（内部の詳
細は図示せず）。このとき、同時に各装置のコー
ナーにモニター用パターン１，２及びチエツク用
パツド３，４，５を形成する。次に、全面に白金
を蒸着法により例えば約1000Åの厚さに被着した
後、窒素雰囲気中で600℃、15分間の熱処理を行
つて、前記配線上並びにモニター用パターン上及
びチエツク用パツド上に白金シリサイド層を形成
する。次いで、王水を用いて未反応の白金を除去
すれば、配線並びにモニター用パターンが完成す
る。尚、第２図の６はアルミニウムのボンデイン
グパツドでその後の工程で形成される。 FIG. 2 shows a preferred embodiment of the invention. A polycrystalline silicon thin film having a thickness of, for example, 5000 Å is formed by CVD on a semiconductor multi-substrate on which necessary impurity diffusion layers and necessary insulating films have been formed. Next, the polycrystalline silicon thin film is patterned using a selective oxidation method to form required wiring in the internal region 7 of each semiconductor device formed on the substrate (internal details are not shown). At this time, monitor patterns 1, 2 and check pads 3, 4, 5 are formed at the corners of each device at the same time. Next, platinum is deposited on the entire surface to a thickness of, for example, about 1000 Å by vapor deposition, and then heat treated at 600°C for 15 minutes in a nitrogen atmosphere to coat the wiring, monitor pattern, and check pad. A platinum silicide layer is formed on the surface. Next, unreacted platinum is removed using aqua regia to complete wiring and monitoring patterns. Note that 6 in FIG. 2 is an aluminum bonding pad which will be formed in a subsequent process.
前記モニター用パターン１及び２は、モニター
しやすいように内部配線の幅に合せて、例えばそ
れぞれ幅4μm、長さ100μm及び幅10μm、長さ
100μmに形成する。チエツク用パツド３，４間又
は４，５間の抵抗値を測定すれば、上記各寸法の
配線抵抗がモニターされる。 The monitor patterns 1 and 2 have a width of 4 μm, a length of 100 μm, a width of 10 μm, and a length of 10 μm, respectively, in accordance with the width of the internal wiring for easy monitoring.
Form to 100μm. By measuring the resistance value between the check pads 3 and 4 or between the check pads 4 and 5, the wiring resistance of each dimension mentioned above can be monitored.
これらのモニター用パターン１，２の抵抗値測
定は、２探針チエツカーとカーブトレーサで容易
にでき、又モニター用パターンの設計上の上限値
を設定しておけば、その抵抗値を測定するだけ
で、金属シリサイド層形成直後に配線の出来、不
出来をモニターできる。そして、もし不良の場合
はその後の工程を止めることができるし、この情
報をフイードバツクして後続ロツトの不良化を防
ぐこともできる。又、前記モニター用パターンを
残しておけば、装置完成後にも抵抗値の測定がで
き、装置の不良解析も容易になる。 Measuring the resistance values of these monitoring patterns 1 and 2 can be easily done using a 2-probe checker and a curve tracer, and if you set the upper limit value in the design of the monitoring patterns, you can simply measure the resistance value. This allows you to monitor the success or failure of wiring immediately after forming the metal silicide layer. If the product is defective, subsequent processes can be stopped, and this information can be fed back to prevent subsequent lots from becoming defective. Furthermore, if the monitoring pattern is left, the resistance value can be measured even after the device is completed, and failure analysis of the device becomes easy.
尚、前記モニター用パターンをスクライブ領域
に形成すれば、装置の集積化に支障をきたすこと
がない。又、上記実施例では白金シリサイドを用
いた場合について説明したが、必要に応じて他の
金属シリサイドを用いる場合も全く同様である。 Note that if the monitor pattern is formed in the scribe area, there will be no problem in integrating the device. Furthermore, although the above embodiments have been described using platinum silicide, the same applies to the case where other metal silicides are used as necessary.
次に金属シリサイド層を有する多結晶シリコン
配線のパターンニング等による広がり効果（減少
も含む）の解析方法を示す。広がり効果をXμm
とすれば、モニター用パターン１の抵抗値R1
（Ω）は、配線の層抵抗をρs（Ω／□）として、
R1＝100／４−Ｘ・ρsとなり、又、モニター用パター
ン２の抵抗値R2（Ω）は、R2＝100／10−Ｘ・ρsとな
る。抵抗値R1、R2を測定すればこれらの２式か
ら装置の製造条件で決定される金属シリサイド層
を有する多結晶シリコン薄膜配線の層抵抗ρ2
（Ω／□）と実効的広がり効果Ｘ（μm）を求める
ことができる。この結果は、次回の装置の設計に
応用できる利点もある。 Next, a method for analyzing the spreading effect (including reduction) due to patterning of polycrystalline silicon wiring having a metal silicide layer will be described. Spreading effect xμm
Then, the resistance value of monitor pattern 1 is R 1
(Ω) is the layer resistance of the wiring as ρs (Ω/□),
R 1 =100/4-X·ρ s , and the resistance value R 2 (Ω) of the monitor pattern 2 is R 2 =100/10–X·ρ s . If the resistance values R 1 and R 2 are measured, the layer resistance ρ 2 of the polycrystalline silicon thin film interconnection having a metal silicide layer is determined from these two equations based on the manufacturing conditions of the device.
(Ω/□) and the effective spreading effect X (μm) can be determined. This result also has the advantage of being applicable to the next device design.
以上説明した様に、本発明の半導体装置の製造
方法は、装置内に金属シリサイド層を有する多結
晶シリコン薄膜配線を形成する際、同時にモニタ
ー用パターンを形成することにより、金属シリサ
イド層形成直後に配線の抵抗値をモニターするこ
とができ、配線の品質を管理して、装置の性能を
向上させるとともに、製造原価を大幅に低減する
ことができる。 As explained above, in the method for manufacturing a semiconductor device of the present invention, when forming a polycrystalline silicon thin film interconnection having a metal silicide layer in the device, a monitoring pattern is formed at the same time, immediately after the metal silicide layer is formed. The resistance value of the wiring can be monitored, the quality of the wiring can be controlled, the performance of the device can be improved, and manufacturing costs can be significantly reduced.
第１図は本発明の原理を示すモニター用パター
ンの平面図、第２図は本発明の一実施例を示す平
面図である。
Ｐ，P′，３，４，５……チエツク用パツド、
１，２……モニター用パターン、６……装置のボ
ンデイングパツド、７……装置の内部領域。
FIG. 1 is a plan view of a monitor pattern showing the principle of the invention, and FIG. 2 is a plan view showing an embodiment of the invention. P, P', 3, 4, 5...Check pad,
1, 2... Monitor pattern, 6... Bonding pad of the device, 7... Internal area of the device.
Claims (1)
た金属シリサイドを配線として用いた半導体装置
の前記配線の評価方法であつて、夫々が多結晶シ
リコン薄膜とその上に形成された金属シリサイド
とからなり、互いに幅が異なりかつ長手方向の両
端部にパツドを有する二つのモニタ素子を設け、
これらモニタ素子の抵抗値をそれぞれ測定し、そ
の測定結果から前記配線の層抵抗と幅の実効的変
化とを評価することを特徴とする半導体装置の評
価方法。1. A method for evaluating the wiring of a semiconductor device using a polycrystalline silicon thin film and a metal silicide formed thereon as wiring, each comprising a polycrystalline silicon thin film and a metal silicide formed thereon, Two monitor elements having different widths and having pads at both ends in the longitudinal direction are provided,
A method for evaluating a semiconductor device, comprising measuring the resistance values of each of these monitor elements, and evaluating effective changes in layer resistance and width of the wiring from the measurement results.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16196479A JPS5683955A (en) | 1979-12-13 | 1979-12-13 | Manufacturing of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16196479A JPS5683955A (en) | 1979-12-13 | 1979-12-13 | Manufacturing of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5683955A JPS5683955A (en) | 1981-07-08 |
| JPH0147011B2 true JPH0147011B2 (en) | 1989-10-12 |
Family
ID=15745410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16196479A Granted JPS5683955A (en) | 1979-12-13 | 1979-12-13 | Manufacturing of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5683955A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6034077A (en) * | 1983-08-04 | 1985-02-21 | Matsushita Electric Ind Co Ltd | Solar cell element and manufacture thereof |
| JPS60177640A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH0680669B2 (en) * | 1985-03-25 | 1994-10-12 | 日本電気株式会社 | Semiconductor device |
| JPS6319833A (en) * | 1986-07-14 | 1988-01-27 | Agency Of Ind Science & Technol | Method for testing semiconductor integrated circuit |
| JPH01125875A (en) * | 1988-10-19 | 1989-05-18 | Matsushita Electric Ind Co Ltd | Solar cell element |
| JPH0851135A (en) * | 1995-06-26 | 1996-02-20 | Seiko Epson Corp | Wafer and verifying method therefor |
| JPH1197645A (en) * | 1997-09-19 | 1999-04-09 | Nec Corp | Semiconductor storage device |
| JP4810741B2 (en) * | 2001-03-23 | 2011-11-09 | 富士ゼロックス株式会社 | Self-scanning light emitting device |
| US7253436B2 (en) | 2003-07-25 | 2007-08-07 | Matsushita Electric Industrial Co., Ltd. | Resistance defect assessment device, resistance defect assessment method, and method for manufacturing resistance defect assessment device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52139383A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Testing method for semiconductor device |
| JPS52155066A (en) * | 1976-06-18 | 1977-12-23 | Mitsubishi Electric Corp | Screening method of thin metal film wirings of semiconductor device |
| JPS53124091A (en) * | 1977-04-05 | 1978-10-30 | Nec Corp | Solid state electron device and its manufacture |
-
1979
- 1979-12-13 JP JP16196479A patent/JPS5683955A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52139383A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Testing method for semiconductor device |
| JPS52155066A (en) * | 1976-06-18 | 1977-12-23 | Mitsubishi Electric Corp | Screening method of thin metal film wirings of semiconductor device |
| JPS53124091A (en) * | 1977-04-05 | 1978-10-30 | Nec Corp | Solid state electron device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5683955A (en) | 1981-07-08 |
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