JPH0851135A - Wafer and verifying method therefor - Google Patents

Abstract

PURPOSE:To save a space by dispersively disposing monitor patterns for verifying semiconductor parameters at a plurality of positions of the four corners of a chip. CONSTITUTION:A functional pad 2 and monitor patterns 3-6 are disposed on the chip 1 of a semiconductor integrated circuit. The patterns 3-6 are dispersively disposed at the four corners of the chip 1 in which the pad 2 is not disposed, thereby eliminating the necessity of a special space for disposing the monitor pattern. When the pad 2 is disposed by avoiding the four corners of the chip 1, a space of the size or more of the pad 2 is obtained at the four corners of the chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor pattern layout for verifying semiconductor parameters such as a threshold voltage of a transistor and a current amplification factor of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, with respect to arrangement of a monitor pattern of a semiconductor integrated circuit, it has been customary to arrange several kinds of monitor patterns such as transistors at a desired location in an arbitrary position such as an outer peripheral portion of a chip. .

[0003]

However, the conventional example has the following drawbacks. A space for arranging the monitor pattern is required, and the chip size will increase accordingly. Since it tries to put the monitor pattern in the restricted space, it is difficult to standardize the pad position of the monitor pattern.

[0004]

The present invention eliminates such drawbacks. The wafer of the present invention is a wafer on which a plurality of semiconductor integrated circuits are formed, and the wafer is the semiconductor integrated circuit. A plurality of semiconductor integrated circuits having a process monitor pattern arranged to calibrate a parameter, the corners of which are adjacent to each other, the process monitor patterns are arranged at the corners of the adjacent semiconductor integrated circuits. To do.

The wafer inspection method of the present invention is a wafer inspection method in which a plurality of semiconductor integrated circuits are formed.
Forming a process monitor pattern for verifying parameters in each of the semiconductor integrated circuits in the corners adjacent to each other, and measuring the monitor patterns arranged in the corners adjacent to each other at once. Is characterized by.

[0006]

EXAMPLES The present invention will be described in detail based on the following examples. FIG. 1 is a schematic diagram of the present invention. Reference numeral 1 denotes a chip outer circumference of the semiconductor integrated circuit. Reference numeral 2 is a functional pad of the semiconductor integrated circuit, and reference numerals 3, 4, 5, and 6 are monitor patterns dispersedly arranged at the four corners of the chip. By arranging the monitor patterns in the four corners of the chip where the pads 2 are not arranged, a special space for arranging the monitor patterns is unnecessary. FIG. 3 is a diagram showing an embodiment of monitor patterns arranged at the four corners of the chip, where 1 is a chip periphery, 2 is a functional pad, 7 is a monitor pad, and 8 is a parameter verification monitor transistor. is there. By arranging the pads 2 so as to avoid the four corners of the chip as described above, at least the space larger than the size of the pad 2 can be secured in the four corners of the chip. Since a monitor pad for monitor pattern verification generally has a size of about ⅓ to ½ of the function pad 2, it is possible to easily adjust the monitor pad position if there are the above-mentioned four corner spaces of the chip. Can be standardized.

Depending on the method of mounting the chip, it may not be possible to place the functional pads at the four corners of the chip. In this case, the present invention is particularly effective.

FIG. 2 shows a monitor pattern arrangement in a wafer state. Even if the monitor patterns are distributed in the four corners of the chip as shown in FIG. 1, the wafer is used to certify the monitor patterns, so that the monitor patterns 3, 4, 5 and 6 are concentrated at one position as shown in FIG. The process monitor pattern is for process management, and the purpose is achieved if data is obtained for each position on the wafer. Therefore, even if different monitor patterns of different chips are concentrated on the wafer, there is no inconvenience, and even if the monitor patterns are dispersed, the measurement can be easily performed. Even if the monitor patterns are arranged in a distributed manner, semiconductor parameters such as threshold voltage and current amplification factor can be measured at once, as in the case where a large monitor pattern is prepared as a result of concentration. Further, since this pattern is formed on the chip, it can be used even after the chip is cut, and process management for each chip can be performed.

[0009]

As described above, according to the present invention, since the monitor patterns can be concentrated on one place, there is an effect that it is possible to provide a wafer whose process measurement is very easy.

Further, according to the wafer inspection method of the present invention, since the process monitor pattern is measured at one time, the number of manufacturing steps can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a chip state according to an embodiment of the present invention.

FIG. 2 is a diagram showing a wafer state.

FIG. 3 is a diagram showing an example of a monitor pattern arranged in a corner of a chip.

[Explanation of Codes] l ... Chip periphery 2 ... Function pads 3-6 ... Monitor pattern 7 ... Monitor pad 8 ... Parameter verification monitor transistor

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Claims (2)

[Claims] 1. A wafer on which a plurality of semiconductor integrated circuits are formed, wherein the wafer has a process monitor pattern arranged to inspect parameters in the semiconductor integrated circuit, and corners thereof are adjacent to each other. A wafer, wherein the plurality of semiconductor integrated circuits have the process monitor patterns arranged at corners adjacent to each other. 2. A wafer certifying method in which a plurality of semiconductor integrated circuits are formed, wherein a plurality of semiconductor integrated circuits whose corners are adjacent to each other are provided at the corners adjacent to each other. A method for certifying a wafer, comprising forming a process monitor pattern for certifying a parameter, and measuring the monitor patterns arranged at the corners adjacent to each other at once.