JPH04288811A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04288811A
JPH04288811A JP7854091A JP7854091A JPH04288811A JP H04288811 A JPH04288811 A JP H04288811A JP 7854091 A JP7854091 A JP 7854091A JP 7854091 A JP7854091 A JP 7854091A JP H04288811 A JPH04288811 A JP H04288811A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
semiconductor
display
address
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7854091A
Other languages
Japanese (ja)
Inventor
Hideo Yamanaka
英雄 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7854091A priority Critical patent/JPH04288811A/en
Publication of JPH04288811A publication Critical patent/JPH04288811A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/54466Located in a dummy or reference die

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To facilitate to analyze defective data and the claims of customers after production and to make it possible of perform quick countermeasures against troubles such as the occurrence of defective products by providing the display for indicating addresses of or areas within a semiconductor wafer in each effective chip of the semiconductor wafer. CONSTITUTION:The position of the orientation flat of a semiconductor wafer 1 is used as the reference of a position, and addresses are imparted to semiconductor chips 4, 4.... Thus, the imparted addresses are indicated. It is preferable to form the display 6 of the address of an aluminum film at the first layer or at the second layer because the display 6 can be observed through a microscope at the stage when the product is formed. the formation of the address display 6 is performed by aluminum photoetching wherein an exposure mask in which the paterns of the address displays 6, 6... of all semiconductor chips 4, 4... are formed is used for the exposure. Or, the own area of a plurality of areas obtained by dividing the inside of the semiconductor wafer into a plurality of parts can be displayed in each effective chip.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置の製造方法
、特に半導体装置の製造後における不良データ、カスタ
マークレームの解析を容易にし、不良品発生等のトラブ
ルに対しての迅速な対応を可能にする半導体装置の製造
方法に関する。
[Industrial Application Field] The present invention facilitates the analysis of semiconductor device manufacturing methods, particularly defective data and customer complaints after semiconductor device manufacturing, and enables prompt response to troubles such as the occurrence of defective products. The present invention relates to a method for manufacturing a semiconductor device.

【0002】0002

【従来の技術】図3は半導体ウェハを示す。図面におい
て、1は半導体ウェハ、2はオリエンテーションフラッ
ト、3、3、…はhFE、抵抗、耐圧等の特性チェック
[1PC(第1回目のペレットチェック)]をするため
のダミーパターンが形成された1PC用ダミーパターン
チップで、真ん中とそのまわり4箇所の併せて5箇所に
設けられている。4、4、…は有効チップ(半導体チッ
プ)となる部分である。5は無効領域であり、ここのチ
ップは製品とはならない。
2. Description of the Related Art FIG. 3 shows a semiconductor wafer. In the drawing, 1 is a semiconductor wafer, 2 is an orientation flat, 3, 3, ... is a 1PC on which a dummy pattern is formed for checking characteristics such as hFE, resistance, breakdown voltage, etc. [1PC (first pellet check)] These dummy pattern chips are provided in 5 locations: the center and 4 locations around it. 4, 4, . . . are portions that become effective chips (semiconductor chips). 5 is an invalid area, and the chip here does not become a product.

【0003】そして、半導体ウェハ1内の各半導体チッ
プのhFE、抵抗、耐圧等の特性は、その5箇所のダミ
ーパターンチップ3、3、…の測定結果に基づいて判断
された。そして、従来、各半導体チップ4、4、…には
そのダミーパターンチップ3、3、…を含め半導体ウェ
ハ1内における自己の位置を示す番号等の表示が全くな
かった。
Characteristics such as hFE, resistance, and breakdown voltage of each semiconductor chip within the semiconductor wafer 1 were determined based on the measurement results of the dummy pattern chips 3, 3, . . . at five locations. Conventionally, each semiconductor chip 4, 4, . . . , including its dummy pattern chips 3, 3, .

【0004】0004

【発明が解決しようとする課題】ところで、従来におい
て、各チップには、半導体ウェハ内における自己の位置
を示す番号等の表示が全くなかったので、半導体装置の
製造後における特性データ、不良データ、カスタマーク
レームの解析を迅速に行うことができず、不良原因等の
追究を迅速に行うことができないという問題があった。 即ち、半導体ウェハ内半導体装置のhFE、抵抗、耐圧
等の特性は、上述した5箇所にある1PC用ダミーパタ
ーンチップ3、3、…を特性測定することにより判断さ
れたが、その5つのチップ3、3、…以外のチップの特
性は測定されない。しかし、ダミーパターンチップ3、
3、…よりも外側のチップの特性は、拡散等においての
温度分布不均一等による不純物濃度不均一、フォトレジ
スト膜の窓開けムラ等の抵抗値バラツキ等によりダミー
パターンチップ3、3、…の特性よりも劣ることが多い
。にも拘らず、ダミーパターンチップ3、3、…の特性
が規格に合格しているとその半導体ウェハの全半導体チ
ップが規格に合格していると判断され出荷される。その
結果、時々カスタマークレームがあった。また、露光用
マスクのパターンの一部に不良があるときは、ダミーパ
ターンチップ3、3、…よりも外側か内側かを問わずそ
の不良に対応した位置にある半導体チップ4に不良が発
生することになる。
[Problems to be Solved by the Invention] Conventionally, each chip did not have any indication of its own position within the semiconductor wafer, such as a number indicating its own position within the semiconductor wafer. There was a problem in that it was not possible to quickly analyze customer complaints, and it was not possible to quickly investigate the cause of defects. That is, the characteristics such as hFE, resistance, breakdown voltage, etc. of the semiconductor device in the semiconductor wafer were determined by measuring the characteristics of the 1PC dummy pattern chips 3, 3, etc. located at the five locations mentioned above. , 3, . . . are not measured. However, dummy pattern chip 3,
The characteristics of the chips outside of dummy pattern chips 3, 3, ... are due to non-uniform impurity concentration due to non-uniform temperature distribution during diffusion, etc., and resistance variations due to uneven opening of photoresist film, etc. It is often inferior to its characteristics. Nevertheless, if the characteristics of the dummy pattern chips 3, 3, . As a result, there were occasional customer complaints. Furthermore, when there is a defect in a part of the pattern of the exposure mask, the defect occurs in the semiconductor chip 4 located at the position corresponding to the defect, regardless of whether it is outside or inside the dummy pattern chips 3, 3, etc. It turns out.

【0005】ところが、ダイシングされ完全に半導体チ
ップ4として独立してしまった段階では、その半導体チ
ップ4が半導体ウエハ1のどの位置に属していたかが判
らないので、半導体チップ4の不良原因を追究するのに
非常に時間がかかり、抜本的改善を迅速に行うことが難
しかった。即ち、不良原因には、例えばある特定の露光
工程のマスクのある部分に問題があるとか、ある拡散装
置に固有の温度分布不均一性があり不良半導体チップの
半導体ウェハ内における位置が解るとすぐに突き止める
ことができるものが少なくない。にも拘らず、各半導体
チップ4、4、…には半導体ウェハ1内における位置を
示す表示がなかったので不良原因の追究に長い時間がか
かり、同じ不良原因を持った半導体チップ4、4、…が
原因が解るまでの長い間出荷され続けるということがな
くはなかった。
However, at the stage where the semiconductor chip 4 is completely independent after being diced, it is not known to which position on the semiconductor wafer 1 the semiconductor chip 4 belongs, so it is difficult to investigate the cause of the failure of the semiconductor chip 4. It was extremely time consuming and difficult to make fundamental improvements quickly. In other words, the cause of the defect may be, for example, a problem with a certain part of the mask in a certain exposure process, or uneven temperature distribution inherent in a certain diffusion device, and as soon as the position of the defective semiconductor chip within the semiconductor wafer is known, There are many things that can be pinpointed. However, since each semiconductor chip 4, 4, ... had no indication indicating its position in the semiconductor wafer 1, it took a long time to investigate the cause of the defect, and the semiconductor chips 4, 4, ... had the same cause of defect. In some cases, the product continued to be shipped for a long time until the cause was determined.

【0006】本発明はこのような問題点を解決すべく為
されたものであり、半導体装置の製造後における不良デ
ータ、カスタマークレームの解析を容易にし、不良品発
生等のトラブルに対する迅速な対応を可能にすることを
目的とする。
The present invention has been made to solve these problems, and it facilitates the analysis of defect data and customer complaints after the manufacture of semiconductor devices, and enables quick response to troubles such as the occurrence of defective products. The purpose is to make it possible.

【0007】[0007]

【課題を解決するための手段】本発明半導体装置の製造
方法は、半導体ウェハの各有効チップ内に該半導体ウェ
ハ内における位置の番地あるいはエリアを示す表示を設
けることを特徴とする。
A method of manufacturing a semiconductor device according to the present invention is characterized in that each effective chip of a semiconductor wafer is provided with an indication indicating the address or area of the position within the semiconductor wafer.

【0008】[0008]

【実施例】以下、本発明半導体装置の製造方法を図示実
施例に従って詳細に説明する。図1(A)、(B)は本
発明半導体装置の製造方法の一つの実施例を説明するた
めのもので、(A)は各半導体チップ4、4、…に与え
られた番地を示すところの半導体ウェハの一部を示す平
面図であり、(B)は番地が形成された半導体チップの
一部を示す平面図である。本半導体装置の製造方法にお
いては、半導体ウェハ1の図1に現われないオリエンテ
ーションフラット(図3の2参照)を位置の基準として
図1の(A)に示すように各半導体チップ4、4、…に
番地を与える。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention will be explained in detail below according to the illustrated embodiments. FIGS. 1(A) and 1(B) are for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 1(A) shows the addresses given to each semiconductor chip 4, 4, . . . FIG. 3B is a plan view showing a part of the semiconductor wafer of FIG. In this semiconductor device manufacturing method, each semiconductor chip 4, 4, . . . as shown in FIG. give a street address.

【0009】そして、各半導体チップ4、4、…にはそ
れぞれ与えられた番地を表示する。図1の(B)は表示
例を示し、6は番地を示す表示である。この番地の表示
6は第1層目あるいは第2層目のアルミニウム膜で形成
すると製品化された段階でも顕微鏡で観察できるので好
ましい。そして、番地表示6の形成は、全半導体チップ
4、4、…分の番地表示6、6、…パターンが形成され
た露光用マスクをつくり、そして、該マスクを露光に用
いたアルミニウムフォトエッチング工程により行う。
[0009]Then, each semiconductor chip 4, 4, . . . displays a given address. FIG. 1B shows a display example, and 6 is a display indicating an address. It is preferable to form the address display 6 using the first or second layer of aluminum film, since this allows observation under a microscope even when the product is manufactured. Then, the formation of the address display 6 is performed by making an exposure mask on which a pattern of address display 6, 6, ... for all the semiconductor chips 4, 4, ... is formed, and then performing an aluminum photo-etching process using the mask for exposure. This is done by

【0010】そして、各半導体チップ4、4、…内にお
ける表示6の位置は、例えば図1の(B)に実線で示す
ようにフォトレジストアライメントマーク7の付近で良
いし、あるいは2点鎖線で示すようにICのタイプを示
す部分付近でも良い。また、マスクナンバーを示す付近
でも良い等、半導体チップ4の回路の形成に支障ないと
ころならどの部分でも良い。また、表示6はアラビア数
字でも良いし、ローマ数字でも良いし、特殊なコードで
あっても良い。
The position of the display 6 in each semiconductor chip 4, 4, . . . may be, for example, near the photoresist alignment mark 7 as shown by the solid line in FIG. As shown, it may be near the part indicating the type of IC. Further, it may be placed anywhere that does not interfere with the formation of the circuit of the semiconductor chip 4, such as near the mask number. Further, the display 6 may be an Arabic numeral, a Roman numeral, or a special code.

【0011】このように本半導体装置の製造方法によれ
ば、半導体ウェハ1の各半導体チップ4、4、…に半導
体ウェハ1内における位置を示す番地表示6を形成した
ので、各半導体チップ4、4、…がペレタイズにより独
立してもその番地表示6から半導体ウェハ1における位
置を認識することができる。従って、カスタマークレー
ムがあったときに不良解析をより迅速に行い、抜本的対
策を迅速に講じ得る。従って、歩留り向上、品質向上を
図ることができる。
As described above, according to the present semiconductor device manufacturing method, since the address marking 6 indicating the position within the semiconductor wafer 1 is formed on each semiconductor chip 4, 4, . Even if 4, . Therefore, when there is a customer complaint, failure analysis can be performed more quickly and drastic measures can be taken quickly. Therefore, it is possible to improve yield and quality.

【0012】図2(A)、(B)は本発明半導体装置の
製造方法の別の実施例を説明するためのもので、(A)
はエリアの設定の仕方を示すウェハ全体の平面図、(B
)は各半導体チップのエリアの付いた番地の設定の仕方
を示すウェハの一部の平面図である。本実施例は、図2
の(A)に示すように、半導体ウェハ1全体をいくつか
、例えば8のエリア(A、B、…H)に分割し、図2の
(B)に示すように、各半導体チップ4、4、…にはそ
のエリア(例えばA)とそのエリア内におけるどの位置
かを示す番号(14)とが番地として与えられている。 そして、図示はしないが図1の実施例の場合と同様に各
半導体チップ4、4、…には自己に与えられた番地(例
えばA14)が所定位置(例えばフォトレジストアライ
メントマーク近傍)に表示されている。尚、各半導体チ
ップ4、4、…に例えばA、B、…等自己が属するエリ
アを示す表示のみを表示するようにしても良い。
FIGS. 2(A) and 2(B) are for explaining another embodiment of the method for manufacturing a semiconductor device of the present invention.
is a plan view of the entire wafer showing how to set the area, (B
) is a plan view of a portion of a wafer showing how addresses with areas of each semiconductor chip are set. This example is shown in Figure 2.
As shown in (A) of FIG. 2, the entire semiconductor wafer 1 is divided into several, for example, eight areas (A, B,...H), and as shown in (B) of FIG. , . . . are given an address as the area (for example, A) and a number (14) indicating the position within the area. Although not shown, as in the embodiment of FIG. 1, each semiconductor chip 4, 4, . ing. Note that each semiconductor chip 4, 4, . . . may display only an indication indicating the area to which it belongs, such as A, B, .

【0013】[0013]

【発明の効果】本発明半導体装置の製造方法は、半導体
ウェハの各有効チップ内に該半導体ウェハ内における位
置あるいはエリアを示す番号を表示することを特徴とす
るものである。従って、本発明半導体装置の製造方法に
よれば、半導体装置製造後においても半導体チップが半
導体ウェハのどこにあるいはどのエリアに位置していた
かが解り、カスタマークレームがあった場合の不良解析
が容易になり、抜本的対策を迅速に行うことが可能にな
る。
The method of manufacturing a semiconductor device of the present invention is characterized in that a number indicating a position or area within the semiconductor wafer is displayed in each effective chip of the semiconductor wafer. Therefore, according to the method for manufacturing a semiconductor device of the present invention, it is possible to know where or in which area the semiconductor chip was located on the semiconductor wafer even after the semiconductor device has been manufactured, making it easier to analyze defects in the event of a customer complaint. It becomes possible to take drastic measures quickly.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】(A)、(B)は本発明半導体装置の製造方法
の一つの実施例を説明するためのもので、(A)は番地
を示す半導体ウェハの平面図、(B)は番地の表示を示
す半導体チップの平面図である。
[Fig. 1] (A) and (B) are for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention, (A) is a plan view of a semiconductor wafer showing an address, and (B) is a plan view of a semiconductor wafer showing an address. FIG. 2 is a plan view of a semiconductor chip showing a display.

【図2】(A)、(B)は本発明半導体装置の製造方法
の他の実施例を説明するためのもので、(A)はエリア
を示す半導体ウェハの断面図、(B)は半導体チップの
エリア付き番地の表示を示す半導体ウェハの平面図であ
る。
[Fig. 2] (A) and (B) are for explaining another embodiment of the method for manufacturing a semiconductor device of the present invention, in which (A) is a cross-sectional view of a semiconductor wafer showing areas, and (B) is a cross-sectional view of a semiconductor wafer. FIG. 2 is a plan view of a semiconductor wafer showing the area-addressed addresses of chips.

【図3】従来例を示す半導体ウェハの平面図である。FIG. 3 is a plan view of a semiconductor wafer showing a conventional example.

【符号の説明】[Explanation of symbols]

1  半導体ウェハ 4  半導体チップ(有効チップ) 6  番地を示す表示 1 Semiconductor wafer 4 Semiconductor chip (effective chip) 6 Display showing address

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  半導体ウェハの各有効チップ内に該半
導体ウェハ内における位置を示す番号を表示することを
特徴とする半導体装置の製造方法。
1. A method for manufacturing a semiconductor device, characterized in that a number indicating a position within the semiconductor wafer is displayed in each effective chip of the semiconductor wafer.
【請求項2】  半導体ウェハの各有効チップ内に該半
導体ウェハ内を複数に分割した複数のエリアのうちの自
己が属するエリアを表示することを特徴とする半導体装
置の製造方法。
2. A method for manufacturing a semiconductor device, characterized in that, in each effective chip of a semiconductor wafer, an area to which the semiconductor wafer belongs is displayed among a plurality of areas obtained by dividing the semiconductor wafer into a plurality of areas.
JP7854091A 1991-03-18 1991-03-18 Manufacture of semiconductor device Pending JPH04288811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7854091A JPH04288811A (en) 1991-03-18 1991-03-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7854091A JPH04288811A (en) 1991-03-18 1991-03-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04288811A true JPH04288811A (en) 1992-10-13

Family

ID=13664749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7854091A Pending JPH04288811A (en) 1991-03-18 1991-03-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04288811A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637156A (en) * 1992-07-14 1994-02-10 Nec Ic Microcomput Syst Ltd Semiconductor device
US6349240B2 (en) 2000-03-27 2002-02-19 Nec Corporation Semiconductor device manufacturing system and method of manufacturing semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637156A (en) * 1992-07-14 1994-02-10 Nec Ic Microcomput Syst Ltd Semiconductor device
US6349240B2 (en) 2000-03-27 2002-02-19 Nec Corporation Semiconductor device manufacturing system and method of manufacturing semiconductor devices
US7054705B2 (en) 2000-03-27 2006-05-30 Nec Electronics Corporation Method of manufacturing semiconductor devices

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