KR20040092554A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to increase reliability of error analysis and to reduce working time in visual processing by forming bridge dummy lines between a dummy word line and a dummy bit line. CONSTITUTION: A semiconductor device includes rectangle active regions(32) arranged to matrix type, word lines(34) elongated vertically to the active region, bit lines elongated horizontally to the active region, a dummy active region(38) formed at outmost of the active regions, at least two dummy word lines(40) formed at outmost of the word lines, and at least two dummy bit lines(42) formed at outmost of the bit lines. The device further includes bridge dummy word lines(41) having constant cell distance formed between the dummy word lines and bridge dummy bit lines(43) having constant cell distance formed between the dummy bit lines.

Description

Semiconductor device

The present invention relates to a semiconductor device of the present invention. In particular, bridge lines are formed on the dummy lines formed at the outer side of the cell block at regular intervals, thereby facilitating the identification of the defect occurrence area, thereby reducing defect detection time and effort. It relates to a semiconductor device.

The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential requirements in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, ~ R = resolution, ~ λ = wavelength of light source, NA = opening number ~]

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV) wavelengths, for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition to these process efforts, a method of changing cell layout design to reduce cell area and achieving high integration has been performed.

DRAM chips also need to be probe tested or packaged once the manufacturing process is complete.

If a defect is generated, the correct cell analysis is performed to check the address of the defective cell in the program of the defective analyzer for accurate failure analysis and recurrence prevention.

However, as the size of the chips increases with the increase in the capacity of DRAM cells, the difficulty of visually detecting the defective cells for failure analysis is increasing.

FIG. 1 is a layout view of a semiconductor device according to the related art, and illustrates an edge portion of a cell block having an area of 8F 2.

First, rectangular active regions 12 are arranged in a matrix on a semiconductor substrate 10 such as a silicon wafer, and word lines 14 are arranged at equal intervals so as to cross two of the active regions 12 one by one. ) Extends in a horizontal direction in a straight line, and bit lines 16 extending in the vertical direction are formed in a space between the active regions 12, and the outermost portions of the active regions 12 are elements. Two unused dummy active regions 18 are formed in a predetermined shape, for example, a comb shape, to prevent abnormal formation of the outermost element, and electrically floated outside the outermost lines of the word lines 14. Two dummy word lines 20 are formed, and two dummy bit lines 22 electrically floated outside the outermost line of the bit line 16 are formed.

The dummy active region 18, the dummy word line 20, and the dummy bit line 22 as described above are not used as elements, but are formed to prevent abnormal formation of the outermost patterns of the repeating patterns.

In the semiconductor device according to the related art as described above, even when a defect is generated in a test process, in order to check the address of the defective cell by visual equipment, it is necessary to sequentially assign a number from the cell block edge to find the corresponding cell. Therefore, it takes a long time, and since there is no identification mark anywhere in the cell block, the corresponding work is performed manually, which makes it difficult to identify defective cells.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form an identification mark on the dummy lines at regular intervals so as to check the address of the defective cell of the chip in which the defect occurs in the test of the chip, and then easily It is to provide a semiconductor device that can find the cell as a visual equipment, it is easy to identify the cause of the failure, and to improve the process yield and the reliability of the device by reducing the failure analysis time.

1 is a layout diagram of a semiconductor device according to the prior art.

2 is a layout diagram of a semiconductor device according to the present invention;

<Description of Symbols for Main Parts of Drawings>

10, 30: semiconductor substrate 12, 32: active area

14, 34: word line 16, 36: bit line

18, 38: dummy active area 20, 40: dummy word line

22, 42: dummy bit line 41: bridge dummy word line

43: bridge dummy bit line

Features of the semiconductor device according to the present invention for achieving the above object,

Rectangular active regions arranged in a matrix,

Word lines extending in a direction crossing the active region;

Bit lines arranged to extend in parallel with the active area in a space between the active areas;

A dummy active area formed outside the outermost of the active areas;

At least two dummy word lines formed on an outermost side of the word lines;

A semiconductor device having at least two dummy bit lines formed on an outermost side of the bit lines.

Bridge dummy word lines formed at regular cell intervals between the dummy word lines;

A bridge dummy bit line is formed between the dummy bit lines at a predetermined cell interval.

Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a layout diagram of a semiconductor device according to the present invention, in which two dummy lines are formed at an edge of a cell block.

First, rectangular active regions 32 are arranged in a matrix on a semiconductor substrate 30 such as a silicon wafer, and word lines 34 are disposed across the active regions 32 in a horizontal direction. Two word lines 34 are disposed across the active region 32, and bit lines 36 are disposed in a vertical direction on an isolation region between the active regions 32.

In addition, the dummy active regions 38 are formed in a shape in which island shapes are repeatedly arranged in a predetermined shape, for example, a comb-shaped integral type, outside the outermost active areas 32 of the cell block, and the outermost word of the cell block. Two dummy word lines 40 are formed to be electrically floated out of the line 34, and the two dummy word lines 40 are spaced apart from each other by a predetermined distance, for example, four island-type dummy active regions ( Bridge word lines 41 are formed one by one on the 32, and two dummy bit lines 42 are formed outside the outermost line of the bit line 36, and the dummy bit lines 42 are formed. The bridge bit lines 43 are formed one by one on a predetermined interval, for example, four comb-shaped dummy active regions 32.

The bridge dummy word lines 41 and the bridge dummy bit lines 43 are formed at regular intervals so that the bridge dummy word lines 41 and the bridge dummy bit lines 43 may be used as identification marks in a step of recognizing a cell of a corresponding address of a defective cell as visual equipment.

Since the bridge dummy word lines 41 and the bridge dummy bit lines 43 are electrically floated, the bridge dummy word lines 41 and the bridge dummy bit lines 43 may be formed at regular intervals, regardless of the positions formed, but may facilitate identification of each other. It can be formed at the position.

As described above, in the semiconductor device according to the present invention, bridge lines are formed at regular intervals between at least two dummy word lines and dummy bit lines formed on the outermost side of the cell block, thereby identifying an indication when using visual equipment. In the analysis process for the defective cells selected by the test process, since the defective cells can be easily found by using the identification mark in the visual operation for the cells of the bad addresses, the reliability of the defect analysis is increased and the visual process is increased. It is possible to reduce the work time in the process, thereby improving the process yield and device reliability.

Claims (1)

Rectangular active regions arranged in a matrix, Word lines extending in a direction perpendicular to the active region; Bit lines arranged to extend in a direction parallel to the active area in a space between the active areas; A dummy active area formed outside the outermost of the active areas; At least two dummy word lines formed on an outermost side of the word lines; A semiconductor device having at least two dummy bit lines formed on an outermost side of the bit lines. Bridge dummy word lines formed at regular cell intervals between the dummy word lines; And a bridge dummy bit line formed at a predetermined cell interval between the dummy bit lines.