JP3223961B2 - Interlayer film flatness measuring function element and interlayer film flatness evaluation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for evaluating the shape of a semiconductor device, and more particularly to a method for evaluating the flatness of an upper and lower wiring interlayer insulating film.

[0002]

2. Description of the Related Art At present, as a method of evaluating the flatness of an interlayer insulating film, a method of confirming a cross-sectional shape by SEM is generally used. However, this method requires the destruction of the wafer, so that it takes a long time to evaluate, the portion that can be evaluated is limited to a small area, and when using a product wafer, it cannot be shipped as a product. . Therefore, a method of easily evaluating the flatness of the interlayer insulating film without destruction has been desired.

As a method for non-destructively evaluating flatness, Japanese Patent Laid-Open Publication No. 1-265532 discloses the following evaluation method. First, an interlayer insulating film is formed on a base polysilicon pattern having various space dimensions, and a metal wiring pattern is formed thereon so as to cross the base polysilicon pattern. Pads are connected to the metal wiring patterns, and a method of monitoring the flatness (flow angle) of an interlayer insulating film by flowing a current between the pads and measuring the conduction of the wiring patterns has been proposed.

Japanese Patent Application Laid-Open No. 5-175304 discloses that
Wiring resistance measurement patterns having the same length are formed on the interlayer insulating film formed on the step pattern and on the interlayer insulating film on which the step pattern is not formed below, and the respective wiring resistance measuring patterns are formed. A method has been proposed in which the wiring resistance is measured, the ratio between the two measured values is calculated, and the flatness of the wiring interlayer insulating film is evaluated based on the calculated value.

[0005]

SUMMARY OF THE INVENTION However, Japanese Patent Laid-Open No.
The evaluation method described in Japanese Patent Application Laid-Open No. 265532 evaluates the flow angle of the interlayer insulating film due to a short circuit between the wirings. There was a problem that it was easily affected. For example, if the etching amount for forming a wiring pattern is a little large, even if the flow angle is large, the wiring material does not remain between the wirings and does not cause a short circuit between the wirings, so that the flow angle is large and the wiring material remains between the wirings. It was sometimes difficult to detect the easy state.

The evaluation method described in Japanese Patent Application Laid-Open No. 5-175304 has room for improvement in that it is not always easy to evaluate flatness by a resistance value. The reason is,
This is because the width of the wiring pattern does not change significantly even when the flatness of the interlayer insulating film is poor because the step of the base and the wiring pattern are orthogonal to each other, and the resistance value does not change to the extent that the difference can be recognized.

The present invention solves the above-mentioned problems of the prior art, and provides a method for evaluating the flatness of an interlayer insulating film, which is hardly affected by other parameters, and for electrically clearly evaluating the difference in flatness. The purpose is to do.

[0008]

According to the present invention, there is provided an element for evaluating the flatness of an interlayer insulating film of a semiconductor device having an upper wiring, a lower wiring, and an interlayer insulating film sandwiched therebetween. A lower wiring pattern comprising two or more lower wirings formed with the same wiring width and wiring interval as the lower wiring, an interlayer insulating film formed on the lower wiring pattern, And an upper layer wiring pattern formed so as to cover the lower layer wiring pattern. By using such a lower wiring pattern, when the flow angle of the interlayer insulating film is large, that is, when the flatness is poor, the upper wiring pattern is greatly lowered between the two lower wiring patterns. , Approaching the underlying wiring pattern. As a result, the capacitance between the upper and lower layers changes, and by measuring the capacitance, the quality of the flow shape of the interlayer insulating film can be evaluated.

Here, the lower wiring pattern, the upper wiring pattern, and the interlayer insulating film of the interlayer film flatness measuring function element are all manufactured under the same film forming conditions and design dimensions as the semiconductor device as a product, and are preferably formed. It is manufactured simultaneously with a semiconductor device to be a product. That is, it is preferably manufactured on the same wafer as the product, and more preferably on the same chip as the product. As a result, the flatness of the interlayer insulating film of the semiconductor device as a product can be accurately evaluated by measuring the flatness of the interlayer insulating film of the interlayer film flatness measuring function element.

In the inter-layer film flatness measuring function element, it is preferable that the lower wiring pattern is formed with two or more kinds of wiring intervals or two or more kinds of wiring widths. In addition, two or more
Formed with a wiring interval of two or more and two or more types of wiring widths
desirable. A semiconductor device usually includes a lower wiring pattern having various wiring widths and wiring intervals. Therefore, the reliability of the evaluation result can be improved by forming the lower layer wiring pattern formed in the interlayer film flatness measuring function element of the present invention with two or more kinds of wiring intervals and wiring widths.

In the above-mentioned interlayer film flatness measuring function element, it is preferable that the lower layer wiring pattern comprises a pair of lower layer wirings formed at a predetermined wiring interval and a predetermined wiring width. With such a configuration, simple and accurate evaluation becomes possible. Further, it is preferable to have a configuration having a plurality of lower wiring patterns having different wiring intervals or wiring widths. In addition, multiple wirings with different wiring intervals and wiring widths
It is preferable to have a configuration having a lower wiring pattern.
No. That is, it is preferable that a plurality of the lower wiring patterns including a pair of lower wirings are provided, each having a different wiring interval and different wiring width. Thereby, the reliability of the evaluation result can be further improved.

According to the present invention, in an interlayer film flatness evaluation method for evaluating the flatness of an interlayer insulating film of a semiconductor device having an upper layer wiring, a lower layer wiring and an interlayer insulating film sandwiched therebetween, Forming a lower wiring pattern composed of two or more lower wirings having the same wiring width and wiring interval as the lower wiring, forming an interlayer insulating film on the lower wiring pattern, and then forming An upper layer wiring pattern is formed so as to cover the lower layer wiring pattern to produce an interlayer film flatness measuring function element, and the capacitance of the interlayer film flatness measuring function element is measured to thereby form the interlayer insulating film of the semiconductor device. The present invention provides an interlayer film flatness evaluation method characterized by evaluating the flatness of an interlayer.

[0013] In the above method for evaluating interlayer film flatness, a plurality of
Of the lower layer wiring pattern, two or more wiring interval or two
It is preferable to form with the above-mentioned wiring width. Also, two or more
It can be formed with the above wiring interval and two or more wiring widths
preferable. This is because the reliability of the evaluation result can be improved.

In the above method for evaluating interlayer flatness,
It is preferable that the lower wiring pattern is formed of a pair of lower wirings formed at a predetermined wiring interval and a predetermined wiring width. This is because simple and accurate evaluation can be performed.
Further, the lower layer wiring pattern composed of the pair of the lower layer wiring, it is desirable to wire spacing or width of the wire form a plurality such that different. Also, the wiring interval and wiring width may differ.
It is desirable to form a plurality of them. This allows
This is because the reliability of the evaluation result can be further improved.

Further, according to the present invention, in the above-mentioned interlayer film flatness evaluation method in which the lower wiring pattern is formed with two or more types of wiring intervals and wiring widths, the same wiring width and lower wiring width as those of the lower wiring are formed on a wafer. After forming a lower layer wiring pattern consisting of a single lower layer wiring formed at a wiring interval, an interlayer insulating film and an upper layer wiring pattern are formed under the same conditions as the above-mentioned interlayer film flatness measuring function element to produce a reference element. Evaluating the flatness of the interlayer insulating film of the semiconductor device by comparing the capacitance of the reference element and the capacitance of the interlayer film flatness measuring function element. A sex evaluation method is provided. As described above, by comparing with the capacitance of the reference element, the influence of the etching conditions and the like can be eliminated, and more accurate evaluation can be performed. It should be noted that the reference element and the interlayer film flatness measuring function element are manufactured under the same film forming conditions and design dimensions except that the single or multiple lower layer wiring is different. Also,
These are preferably produced simultaneously.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG.
In the preferred embodiment of the present invention, the lower wiring pattern is formed of a metal, a semiconductor, or a laminated material thereof. As the metal material, a material used in a product pattern such as aluminum or an aluminum alloy containing impurities such as silicon and copper is used. As a semiconductor or a stacked material of a semiconductor and a metal, a material used in a product pattern such as polysilicon, polysilicon doped with impurities, or a stacked metal material such as tungsten on these semiconductor materials is used. Further, the wiring width and the wiring interval are designed to be the same as those of the semiconductor device as a product. For example, a wiring width of 0.3 to 1.
0 μm, and the wiring interval is 0.1 to 2.0 μm.

The interlayer insulating film is an oxide film, a nitride film, BPSG
For example, a material used for a semiconductor device to be a product is used. The upper layer wiring pattern uses the same material as that used in the product similarly to the lower layer wiring pattern.

The upper wiring pattern is formed so as to cover the lower wiring pattern formed with a predetermined wiring width and a predetermined wiring interval.
It is possible to accurately measure the capacitance of an interlayer film flatness measuring function element.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS. Hereinafter, a pattern for evaluation is formed on the same chip simultaneously with the formation of the semiconductor device product.

After the lower wiring pattern 1 is formed, an interlayer insulating film 2 is formed thereon. Next, as shown in FIG. 2, a hole 7 in the insulating film for connecting the capacitance measuring pad 6 formed in the upper wiring pattern is opened on the capacitance measuring pad 5 in the lower wiring pattern. .

Next, the upper wiring pattern 3 is formed so as to straddle the two lower wiring patterns. At this time, a pad 6 ′ of the upper wiring pattern for connecting to the lower wiring pattern is formed directly above the capacitance measuring pad 5 of the lower wiring pattern through the upper and lower wiring connection holes 7 of the interlayer insulating film.

Finally, pads 6 and 6 'of the upper wiring pattern
Is used as an electrode, the capacitance of the interlayer insulating film 2 sandwiched between the lower wiring pattern 1 and the upper wiring pattern 3 is measured, and the static electricity of the reference element formed as a single lower wiring pattern by the same method. The flatness of the interlayer insulating film is evaluated by comparing with the capacitance.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

In this embodiment, as shown in FIG.
Use copper-containing aluminum as wiring material, 0.5μm,
l. A lower wiring pattern 1 having a wiring width of 0.5 μm and a wiring length of 100 μm is formed simultaneously with a product pattern at intervals of 0 μm and 1.5 μm.

Next, an interlayer insulating film such as an oxide film, a nitride film, a BPSG, etc. is grown to a thickness of 5000.degree. And a flow is performed by heat treatment. The hole 7 is opened. Next, the wiring width is 1.5 μm, 2.0 μm, respectively, so as to straddle the two lower wiring patterns using the same wiring material aluminum as the lower wiring material.
An upper wiring pattern is formed with a thickness of 2.5 μm.

In the upper wiring pattern, the capacitance measuring pad 6 directly connected to the wiring pattern and the capacitance measuring pad 6 in the upper wiring pattern are provided immediately above the capacitance measuring pad 5 in the lower wiring pattern. 'Is located. The pad 6 ′ is connected to the pad 5 of the underlying wiring pattern through the upper and lower wiring connection holes 7. The size of the pad is 20 × 20 μm.

Next, a protective film such as a nitride film or polyimide is formed on the upper aluminum wiring pattern, and holes are formed on the pads 6 and 6 'of the upper wiring pattern.

The capacitance of the interlayer film flatness measuring function element manufactured as described above is measured by bringing a probe into contact with the pads 6 and 6 'of the upper wiring pattern. The measured value is compared with the measured value of the capacitance of the reference element as a reference value to evaluate the interlayer film flatness. The reference element is provided with a lower wiring pattern composed of a single lower wiring having a wiring width of 0.5 μm and an upper wiring pattern composed of a single upper wiring having a wiring width of 0.5 μm. By using the reference element as described above, the influence on the capacitance value due to the thickness of the interlayer insulating film can be removed. When the flatness of the interlayer insulating film is poor, the upper wiring lowers between the two lower wirings, thereby approaching the lower wiring pattern. Becomes large, and the poor flatness can be electrically detected (FIG. 1).

In this embodiment, the case where the wiring material is copper-containing aluminum has been described. However, pure aluminum, aluminum with silicon, aluminum with silicon and copper, polysilicon, polysilicon doped with impurities, tungsten, etc. are used as necessary. Or a material obtained by stacking tungsten or the like on polysilicon or polysilicon doped with impurities can be used.

The wiring width and the wiring interval can be set as required. Further, the accuracy of capacitance measurement can be improved by increasing the wiring length.

[0031]

As described above, according to the present invention,
The flatness of the interlayer insulating film is evaluated by measuring the capacitance by using a flatness measuring function element in which upper and lower layer wiring patterns are formed with the interlayer insulating film interposed therebetween. It can be evaluated easily and electrically with high precision.

By setting the wiring width and the wiring interval of the lower wiring pattern to several types, the flatness of the interlayer insulating film can be measured at the wiring interval in consideration of the product pattern, and the reliability of the evaluation result can be improved.

Further, by using a reference device manufactured under the same film forming conditions and design dimensions as the interlayer film flatness measuring function element, the flatness of the interlayer insulating film can be improved, and the etching conditions for forming a wiring pattern can be improved. Can be measured without being affected by other parameters, and an accurate evaluation result can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing one example of an interlayer insulating film flatness measuring function element of the present invention.

FIG. 2 is a plan view illustrating an example of an interlayer insulating film flatness measuring function element according to the present invention.

FIG. 3 is a plan view illustrating an example of an interlayer insulating film flatness measuring function element according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lower wiring pattern 2 Interlayer insulating film 3 Upper wiring pattern 4 Capacitance measuring device 5 Lower wiring pattern capacitance measuring pad 6 Upper wiring pattern capacitance measuring pad 6 'Upper wiring pattern capacitance measuring pad 7 Upper and lower layer wiring connection holes

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/66 H01L 21/3205

Claims (13)

(57) [Claims] The flatness of an interlayer insulating film of a semiconductor device having an upper wiring, a lower wiring and an interlayer insulating film sandwiched therebetween is determined by measuring a capacitance between the upper wiring and the lower wiring. An element to be evaluated, comprising: a lower wiring pattern including two or more lower wirings formed with the same wiring width and wiring interval as the lower wiring; an interlayer insulating film formed on the lower wiring pattern; An interlayer film flatness measuring function element comprising: an insulating film; and an upper wiring pattern formed so as to cover the lower wiring pattern. 2. The interlayer film flatness measuring function element according to claim 1, wherein the lower wiring pattern is formed with two or more kinds of wiring intervals or two or more kinds of wiring widths. 3. The method according to claim 1, wherein the lower wiring pattern comprises two or more wiring patterns.
Formed with line spacing and two or more types of wiring width
The functional element for measuring the flatness of an interlayer film according to claim 1. 4. The device according to claim 1, wherein the lower wiring pattern comprises a pair of lower wirings formed with a predetermined wiring interval and a predetermined wiring width. 5. a plurality of the lower layer wiring pattern composed of the pair of the lower layer wiring, the plurality of lower-layer wiring patterns,
The functional element for measuring the flatness of an interlayer film according to claim 4 , wherein each of the wiring elements has a different wiring interval or wiring width. 6. a plurality of the lower layer wiring pattern composed of the pair of the lower layer wiring, the plurality of lower-layer wiring patterns,
5. The functional element for measuring interlayer film flatness according to claim 4 , wherein the element has a different wiring interval and different wiring width. 7. An interlayer film flatness evaluation method for evaluating the flatness of an interlayer insulating film of a semiconductor device having an upper wiring, a lower wiring, and an interlayer insulating film sandwiched between the lower wiring and a lower wiring. Forming a lower wiring pattern composed of two or more lower wirings having the same wiring width and wiring interval, forming an interlayer insulating film on the lower wiring pattern, and covering the lower wiring pattern on the interlayer insulating film; The upper layer wiring pattern is formed as described above to produce an interlayer film flatness measuring function element, and the flatness of the interlayer insulating film of the semiconductor device is evaluated by measuring the capacitance of the interlayer film flatness measuring function element. A method for evaluating the flatness of an interlayer film. 8. the lower layer wiring pattern, an interlayer film flatness evaluation method according to claim 7, characterized in that formed in more than one wiring interval or two or more wiring width. 9. The semiconductor device according to claim 9, wherein said lower wiring pattern comprises two or more wiring patterns.
It is characterized by being formed with a line interval and two or more types of wiring width.
The method for evaluating the flatness of an interlayer film according to claim 7. Wherein said lower layer wiring pattern, an interlayer film flatness evaluation method according to claim 7, characterized in that a pair of the lower layer wiring formed in a predetermined wire spacing and wire width. 11. interlayer film flatness evaluation method according to claim 10, the lower layer wiring pattern composed of the pair of the lower layer wiring, wire spacing or width of the wire, characterized in that a plurality of formed such that different. 12. The lower layer comprising the pair of lower wirings
Adjust the wiring pattern so that the wiring interval and wiring width are different.
The interlayer according to claim 10, wherein a plurality of layers are formed.
Film flatness evaluation method. 13. After forming a lower wiring pattern composed of a single lower wiring formed with the same wiring width and wiring interval as the lower wiring on the wafer, the same conditions as those of the interlayer film flatness measuring function element are used. Forming an interlayer insulating film and an upper layer wiring pattern to produce a reference element, and comparing the capacitance of the reference element with the capacitance of the interlayer film flatness measuring function element, 13. The method for evaluating the flatness of an interlayer film according to claim 8, wherein the flatness of the interlayer insulating film is evaluated.