JPS6319833A - Method for testing semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To quickly select good quality chips by irradiating only the test circuit included in semiconductor integrated circuit with the X-ray and then executing electrical characteristic test for test circuit. CONSTITUTION:The radioactive ray test is carried out for the radiation resistance measuring element of chip by irradiating a wafer 1 fixed on a wafer chuck 12 from the upper part of wafer 1 with the X-ray which is restricted in the irradiation region by the apertures 15 and 14. In this case, damage by X-ray of measuring element is accelerated by applying volage to a measuring element through a bonding pad using a probe 13. Therefore, first, a wafer is fixed, the initial characteristic before irradiation of X-ray is evaluated for the element to be measured, the measuring element is irradiated with the X-ray with low irradiation amount by applying a voltage to carry out experiment of X-ray irradiation corresponding to the specified amount of irradiation of X-ray. In this case, exposure to X-ray of integrated circuit by scattering is minimized, thereafter electrical characteristic after irradiation is tested to give the result of good or no-good. The test is then repeated to the subsequent chips.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to radiation resistance testing of semiconductor integrated circuits, and more particularly to a testing method for semiconductor integrated circuits that allows radiation testing in a wafer state.

[Background of the invention]

Conventionally, when testing the radiation resistance of semiconductor integrated circuits, a chip containing the semiconductor integrated circuit is assembled into a package and C06
Radiation was performed using a 0 grade gamma ray irradiation facility, and then electrical characteristics tests were conducted. Such conventional methods not only require large-scale irradiation facilities but also require long testing times, which delays the feedback of test results to the manufacturing process and makes gamma-ray testing a kind of destructive process. Since this is a test, only sampling inspection of chips assembled into packages is possible, and it is not possible to pass or pass the lot.
The disadvantage was that failure could only be determined statistically. Regarding testing methods for electrical semiconductor devices,
An example is described in JP-A-57-34344.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit testing method that eliminates the above-mentioned drawbacks and allows rapid and simple selection of radiation-resistant semiconductor integrated circuits in wafer state.

[Summary of the invention]

Semiconductor devices used in geostationary satellites and the like need to be tested for ionizing radiation resistance. This tolerance test is conducted using highly transparent gamma rays. However, gamma ray facilities are large-scale facilities, and it is difficult to install them close to semiconductor manufacturing lines. Therefore, we investigated the possibility of carrying out a tolerance test using the X-ray source used as a single diffraction device.

As a result, as shown in FIG. 1, it was found that there is a proportional relationship between the X-ray irradiation amount and the gamma-ray absorption line pattern, and it was found that an X-ray device can be used instead.

In this case, in the conventional radiation resistance test using gamma rays, pass/fail was determined by sampling inspection, and direct chip inspection was not possible, so we also considered the possibility of testing all chips in the wafer state.

When conducting a radiation resistance test in a wafer state, it is necessary to limit the radiation irradiation range and irradiate only the test element. Therefore, if the product and the irradiated circuit are placed in the same chip on a wafer and the radiation tolerance test is performed by irradiating only the irradiated circuit with X-rays, it becomes possible to pass/fail each chip on the wafer. . In this case, it is necessary to provide a certain distance between the irradiated circuit and the product with respect to the spatial distribution of the irradiated Xa.

Regarding the test method, as shown in Figure 2, MO
In the case of SFET, it has been found that when a radiation irradiation experiment is performed while applying a positive voltage, device characteristics such as threshold voltage change Δv th and interface state density ΔDjt progress. Therefore, in MOSFET, elements to which a positive voltage is applied deteriorate more rapidly than elements to which no voltage is applied, so if voltage is applied only to the radiation tolerance measurement element to accelerate characteristic deterioration, the product will be This makes it possible to conduct tests while minimizing radiation exposure to integrated circuits.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. In a chip 2 formed on a wafer 1, an integrated circuit 3 and a radiation resistance measurement element 4, which will become a product, are formed. The measuring element 4 is
This element detects the radiation resistance of the integrated circuit 3, is composed of transistors, and undergoes an X-ray irradiation test. Therefore, in order to prevent the integrated circuit 3 from being irradiated with X-rays, the measurement element 4 is designed and laid out at a distance d or more from the integrated circuit 3 included in the same chip or peripheral chips. As shown in FIG. 4, this distance d is defined as the shortest distance between the transistor included in the integrated circuit 3 and the measuring element 4, and is required to be 1 mm or more for the X-ray irradiation test. Note that the measurement element 4 is provided with wiring and a bonding butt 6 for conducting an electrical property test.

Next, the test method will be explained using FIG. 5. Fourth
The figure shows a schematic cross-sectional view of an automatic prober for X-ray tests. An X beam is applied to the wafer 1 fixed on the wafer chuck 12 from above the wafer 1, the irradiation area of which is limited by the aperture 15.14.
By irradiating the radiation with radiation, it is possible to perform a radiation test on the radiation tolerance measurement element in a certain chip. At this time, a voltage is applied to the measuring element through the bonding pad using the probe needle 13 to accelerate X-ray damage to the measuring element. FIG. 6 shows a flowchart of the measurement. First, the wafer is fixed, and an initial characteristic evaluation of the device to be measured is performed before X-ray irradiation. Next, apply a voltage to the measurement element,
Performs low dose X-ray irradiation, xL equivalent to the specified X-ray dose
Conduct the A irradiation experiment.

At this time, since the amount of X-ray irradiation is low, exposure to radiation due to scattering, etc. to the integrated circuit that will become the product can be suppressed to a minimum. After that, the electrical characteristics after irradiation are tested, a pass/fail judgment is made, and the test is repeated for the next chip.

・) A second embodiment of the present invention will be described using FIG. 7. As in the first embodiment, a chip formed in a wafer contains an integrated circuit that will become a product and radiation! ,.

A line resistance measurement element 4 is formed. At this time, a region 32 for forming passive circuit components such as resistors and capacitors in the integrated circuit is formed adjacent to the measuring element 4. The distance d between the region 31 including the active element and the plurality of measurement elements 4 is set to be 1 mn+ or more.

According to this embodiment, by forming the passive circuit component formation region 32 with high radiation resistance between the region 31 containing the active element and the measuring element 4, the area of the elements within the chip can be effectively utilized. In particular, in the case of a master sliced chip, a resistive element or the like can be formed adjacent to the radiation tolerance measuring element 4.

〔Effect of the invention〕

According to the present invention, since radiation tolerance tests can be performed on the wafer, the test time is shortened compared to conventional gamma ray irradiation experiments, and it is possible to test all chips instead of sampling them.

To describe the effect specifically, in the conventional test, a sample was assembled into a package and 106ra of C060 was used.
It used to take 24 hours just for irradiation to perform a d-irradiation test, but in an X-ray test, irradiation can be performed in about 10 minutes.
It went to the production line.

[Brief explanation of drawings]

Figure 1 is a diagram showing the relationship between γ-ray absorption and X-ray irradiation amount;
FIG. 2 is a diagram showing the relationship between the applied voltage VC, the change in threshold voltage ΔVth, and the change in interface state density ΔD jt during voltage application irradiation, and FIG. A diagram showing an embodiment of Section 1 of the present invention in which a radiation tolerance measuring element is mounted on a chip, FIG. 4 is a diagram showing the distance relationship between the measuring element and the integrated circuit, and FIG. 5 is a cross-sectional view of the X-ray irradiation device. FIG. 6 is a diagram showing the structure, and FIG. 6 is a flowchart for determining radiation resistance X and atIl, and FIG. 7 is a diagram showing a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Wafer, 2... Chip, 3... Integrated circuit element to become a product, 4... Element for measuring radiation tolerance, 5... Scribe line, 6... Bonding pad, 12...
...Wafer chuck, 13...Probe needle, 14.1
5... Aperture, 16... X-ray blocking layer, 31...
Integrated circuit area including active elements, 32... Integrated circuit area formed only by passive circuit elements No. 70 4) Z

Claims (1)

[Claims] 1. A functional circuit equipped with input/output terminals and having a predetermined function;
A semiconductor integrated circuit that includes, in the same chip, a test element or a test circuit that is provided with input/output terminals independent of the functional circuit and that is formed at a distance of 1 mm or more from all active elements included in the functional circuit. In contrast, the semiconductor integrated circuit is characterized in that only the test circuit included in the semiconductor integrated circuit is irradiated with X-rays, and then the test circuit is subjected to an electrical characteristic test to select non-defective chips. test method.