CN116895548A - Method for online monitoring stress through PCM (pulse code modulation) test - Google Patents

Method for online monitoring stress through PCM (pulse code modulation) test Download PDF

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Publication number
CN116895548A
CN116895548A CN202310709688.XA CN202310709688A CN116895548A CN 116895548 A CN116895548 A CN 116895548A CN 202310709688 A CN202310709688 A CN 202310709688A CN 116895548 A CN116895548 A CN 116895548A
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Prior art keywords
pcm
stress
pcm test
test
dielectric layer
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Inventor
刘勇
谭磊
徐侧茗
王斌
肖添
施杨剑
兰贵明
邓建国
王飞
湛逍逍
徐岚
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Chongqing Zhongke Yuxin Electronic Co ltd
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Chongqing Zhongke Yuxin Electronic Co ltd
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Priority to CN202310709688.XA priority Critical patent/CN116895548A/en
Publication of CN116895548A publication Critical patent/CN116895548A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/18—Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention discloses a method for monitoring stress on line through PCM test, comprising the following steps: 1) Forming a plurality of PCM test regions (3) on a semiconductor substrate (1); 2) Forming a first metal region (5) at both ends of the PCM test region (3) of step 1); 3) Performing a first PCM test and recording the resistance value of each PCM test zone (3); 4) Covering an ith dielectric layer (6) on the PCM test area (3); the initial value of i is 1; 5) Forming an (i+1) th metal region (7) at two ends of the PCM test region (3) in the step 4) and connecting with the (i) th metal region (5); 6) Performing an i+1th time of PCM test, and recording the resistance value of each PCM test area (3); 7) The semiconductor wafer stress is calculated based on the resistance value of each PCM test zone (3) at the i+1th PCM test and the i-th PCM test. The invention realizes the on-line stress monitoring of the product wafer.

Description

Method for online monitoring stress through PCM (pulse code modulation) test
Technical Field
The invention relates to the field of semiconductor device and integrated circuit manufacturing, in particular to a method for monitoring stress on line through a PCM test.
Background
In the process of manufacturing semiconductor devices and circuits, wafers are deformed and accumulate stress due to a plurality of factors such as films attached to surfaces, high temperature processes, use of high temperature jigs, doping, and the like. If this stress occurs in the core region of the semiconductor device and circuit, it can cause a change in the band structure of the region and cause a change in parameters such as carrier concentration, carrier effective mass, mobility, etc., which ultimately affect the electrical performance of the device and circuit.
For chip manufacture, the influence of the insulating dielectric film and metal wiring deposited at the rear section of the manufacturing process on the electrical performance of devices and circuits is particularly obvious, and particularly, the electrical parameters of the semiconductor devices and circuits can be changed before and after thinning, before and after gold backing, before and after dicing and before and after packaging, and the products can be disqualified when serious. It is therefore necessary to monitor the stress at these stages.
In the process of monitoring stress in the semiconductor manufacturing process, the stress accumulated after the silicon wafer passes through a certain process is calculated and represented by placing a graphic accompanying sheet and testing the warpage related parameters of the accompanying sheet before and after the accompanying sheet passes through the certain process. The method can only generally reflect the overall stress condition of the accompanying sheet, and cannot represent the actual stress condition of a certain local position of the product sheet.
Disclosure of Invention
The invention aims to provide a method for online monitoring stress through a PCM test, which comprises the following steps:
1) Forming a plurality of PCM test regions on a semiconductor substrate;
2) Forming an ith metal area at two ends of the PCM test area in the step 1), wherein the initial value of i is 1;
3) Performing the ith PCM test and recording the resistance value of each PCM test area;
4) Covering an ith dielectric layer on the PCM test area;
5) Forming an (i+1) th metal region at two ends of the PCM test region in the step 4), and connecting the (i) th metal region;
6) Performing the (i+1) th PCM test, and recording the resistance value of each PCM test area;
7) Calculating the stress increment of the semiconductor wafer based on the resistance value of each PCM test area in the (i+1) th PCM test and the (i) th PCM test, wherein the stress increment comprises the stress increment introduced into the semiconductor substrate by the (i) th dielectric layer;
8) Let i=i+1 and repeat steps 2) to 7), the semiconductor wafer stress increase that occurs after each metal region formation is measured until the semiconductor device fabrication is completed.
Further, the PCM test region includes a resistive region or a MOS transistor channel region.
Further, the methods for forming the PCM test regions include an implantation doping method and a diffusion doping method, and the doping types include: n-type, P-type, a combination of N-type and P-type.
Further, the ith dielectric layer comprises an IMD dielectric layer, an ILD dielectric layer, an isolated metal layer and a passivation film layer.
Further, when i is greater than or equal to 2, the stress increment of the semiconductor wafer further comprises a stress increment introduced into the semiconductor substrate when the 1 st dielectric layer, the … th dielectric layer and the i-th dielectric layer are used together.
Further, when a thinning process is involved in fabricating a semiconductor chip using a semiconductor substrate, the following steps are also performed:
s 1) performing a jth PCM test, and recording the resistance value of each PCM test area;
s 2) performing a thinning process;
s 3) performing the j+1th PCM test, and recording the resistance value of each PCM test area;
s 4) calculating the stress increment introduced to the semiconductor substrate by the thinning process based on the resistance value of each PCM test area in the j+1th and j th PCM tests.
Further, when a back gold process is involved in fabricating a semiconductor chip using a semiconductor substrate, the following steps are also performed:
s 1) performing a kth PCM test, and recording the resistance value of each PCM test area;
s 2) executing a gold backing process;
s 3) carrying out the k+1th PCM test, and recording the resistance value of each PCM test area;
s 4) calculating the stress increment introduced to the semiconductor substrate by the back-metal process based on the resistance value of each PCM test zone at the (k+1) th and the (k) th PCM tests.
Further, the increment of the stress introduced to the semiconductor substrate by the ith dielectric layer is characterized by the difference between the resistance values of the same PCM test area at the (i+1) th and the (i) th PCM tests.
Further, the semiconductor wafer stress further comprises a stress increment to which the ith dielectric layer is subjected.
Further, the method for calculating the stress of the ith dielectric layer comprises the following steps: and taking the negative of the stress increment value introduced into the semiconductor substrate by the ith dielectric layer based on the force interaction principle to obtain the stress increment received by the ith dielectric layer.
The invention designs a plurality of doped resistor strips or a plurality of MOS devices distributed along a specific crystal direction to test and calculate stress based on the piezoresistive property of silicon, and applies the doped resistor strips or the MOS devices to the manufacturing stage of semiconductor devices and circuits to characterize the stress of dielectric films, conductive layers and silicon surfaces on line, thereby realizing the on-line stress monitoring of the product wafer.
Drawings
FIG. 1 is a schematic diagram of a stress test using the method of the present invention;
FIG. 2 is an 8-element bipolar resistor layout;
fig. 3 is a 4-element bipolar resistor layout.
In the figure: the semiconductor substrate 1, a first dielectric masking layer 2, a PCM test region 3, a second dielectric masking layer 4, an ith metal region 5, an ith dielectric layer 6, an (i+1) th metal region 7 and a passivation layer 8.
Detailed Description
The present invention is further described below with reference to examples, but it should not be construed that the scope of the above subject matter of the present invention is limited to the following examples. Various substitutions and alterations are made according to the ordinary skill and familiar means of the art without departing from the technical spirit of the invention, and all such substitutions and alterations are intended to be included in the scope of the invention.
Example 1:
referring to fig. 1, a method of on-line monitoring stress by PCM testing includes the steps of:
1) Forming a plurality of PCM test regions 3 on a semiconductor substrate 1;
2) Forming an i-th metal region 5,i at the two ends of the PCM test region 3 of the step 1) with an initial value of 1;
3) Performing the ith PCM test and recording the resistance value of each PCM test area 3;
4) Covering the ith dielectric layer 6 on the PCM test area 3;
5) Forming an (i+1) th metal region 7 at two ends of the PCM test region 3 in the step 4) and connecting with the (i) th metal region 5;
6) Performing the (i+1) th PCM test, and recording the resistance value of each PCM test area 3;
7) Calculating the stress increment of the semiconductor wafer based on the resistance value of each PCM test area 3 in the (i+1) th PCM test and the (i) th PCM test, wherein the stress increment comprises the stress increment introduced into the semiconductor substrate 1 by the (i) th dielectric layer 6;
8) Let i=i+1 and repeat steps 2) to 7), the semiconductor wafer stress increase that occurs after each metal region formation is measured until the semiconductor device fabrication is completed.
Example 2:
the method for on-line monitoring stress by PCM testing has the same technical content as in embodiment 1, and further, the semiconductor substrate 1 and the PCM test region 3 are semiconductors with opposite doping types.
Example 3:
a method for on-line monitoring stress by PCM testing, the technical content of which is the same as any one of embodiments 1-2, further, the PCM test region 3 comprises a resistor region or a MOS transistor channel region.
Example 4:
a method for on-line monitoring stress by PCM testing, the technical content of which is as in any one of embodiments 1-3, further comprising the step of forming a plurality of PCM test regions 3 on a semiconductor substrate 1, comprising:
1.1 Forming a first dielectric masking layer 2 on the semiconductor substrate 1 to avoid entry of impurities into other places than the test region (3) when the test region (3) is formed;
1.2 A plurality of PCM test regions 3 are formed.
Example 5:
a method for on-line monitoring stress by PCM testing, the technical content of which is as in any of examples 1-4, further, the dielectric masking layer 2 is typically a silicon dioxide dielectric thermally grown in compliance with the processing, and may be a composite dielectric film, insulating, depending on the process flow.
Example 6:
a method for online monitoring stress by PCM testing, the technical content of which is as in any one of embodiments 1-4, further comprising, before covering the ith dielectric layer 6 over the PCM test zone 3, covering the second dielectric masking layer 4 over the PCM test zone 3 such that the second dielectric masking layer 4 is located between the PCM test zone 3 and the ith dielectric layer 6.
Example 7:
a method for on-line monitoring stress by PCM testing, the technical content of which is as in any of examples 1-6, further, the masking layer 4 is typically thermally grown thin silicon dioxide, which is used as a masking layer for doping implantation to reduce silicon surface damage.
Example 8:
a method for on-line monitoring of stress by PCM testing, the technical content of which is as in any of examples 1-7, further, if diffusion doping is used, it is not necessary to form the masking layer 4 prior to doping.
Example 9:
the method for online monitoring stress by PCM test has the technical content as in any one of embodiments 1-7, and further, after the metal region is manufactured, the passivation layer 8 is covered on the front surface of the semiconductor device obtained by processing the integrated circuit, so as to protect the circuit from being contaminated by external water vapor and metal ions.
The passivation layer 8 is the last layer on the front side of the semiconductor device.
Example 10:
the method for online monitoring stress through PCM testing has the technical content as in any one of embodiments 1 to 4, further, the forming manner of the plurality of PCM test regions 3 includes an implantation doping manner and a diffusion doping manner, and the doping types include: n-type, P-type, a combination of N-type and P-type.
Example 11:
the method for online monitoring stress through PCM testing has the technical content as in any one of embodiments 1-5, further, the ith dielectric layer 6 includes an IMD dielectric layer, an ILD dielectric layer, an isolated metal layer, and a passivation film layer.
Example 12:
the method for online monitoring stress through PCM testing has the technical content as in any one of embodiments 1 to 5, further, when i is greater than or equal to 2, the stress increment of the semiconductor wafer further comprises a stress increment introduced into the semiconductor substrate 1 when the 1 st dielectric layer, the … th dielectric layer and the i-th dielectric layer are used together.
Example 13:
a method for in-line monitoring stress by PCM testing, the technical content of which is as in any of embodiments 1-6, further comprising, when a thinning process is involved in the fabrication of a semiconductor chip from a semiconductor substrate 1, the steps of:
s 1) performing a jth PCM test and recording the resistance value of each PCM test zone 3;
s 2) performing a thinning process;
s 3) performing the j+1th PCM test, and recording the resistance value of each PCM test zone 3;
s 4) calculating the stress delta introduced to the semiconductor substrate 1 by the thinning process based on the resistance value of each PCM test section 3 at the j+1th PCM test and the j-th PCM test.
Example 14:
a method for on-line monitoring of stress by PCM testing, the technical content of which is as in any of embodiments 1-6, further comprising, when a back gold process is involved in the fabrication of a semiconductor chip from a semiconductor substrate 1, the steps of:
s 1) performing a kth PCM test and recording the resistance value of each PCM test zone 3;
s 2) executing a gold backing process;
s 3) performing the (k+1) th PCM test, and recording the resistance value of each PCM test area 3;
s 4) calculating the stress delta introduced to the semiconductor substrate 1 by the back gold process based on the resistance value of each PCM test zone 3 at the k+1th PCM test and the kth PCM test.
Example 15:
a method for online monitoring stress by PCM testing, which is as described in any of embodiments 1 to 8, further, wherein the increment of stress introduced into the semiconductor substrate 1 by the ith dielectric layer 6 is characterized by the difference between the resistance values of the same PCM test zone 3 at the i+1th PCM test and the i PCM test.
Example 16:
the method for online monitoring stress through PCM testing has the technical content as in any one of embodiments 1 to 9, and further, the stress of the semiconductor wafer further includes a stress increment to which the i-th dielectric layer 6 is subjected.
Example 17:
the method for online monitoring stress through PCM testing has the technical content as in any one of embodiments 1 to 10, and further, the method for calculating the stress of the ith dielectric layer 6 includes: based on the force interaction principle, the stress increment value introduced into the semiconductor substrate 1 by the ith dielectric layer 6 is taken as negative, so that the stress increment suffered by the ith dielectric layer 6 is obtained.
Example 18:
a method of on-line monitoring stress by PCM testing, comprising the steps of:
1) A plurality of resistive regions 3 are formed on the semiconductor substrate 1. The plurality of resistor areas 3 are regularly distributed according to the stress test requirement, such as the 8-element bipolar resistor shown in fig. 2 and the 4-element bipolar resistor layout shown in fig. 3.
2) The first metal region 5 is formed in the resistive region 3 in sequence following the flow of the process stage used.
3) A first PCM test is performed and the resistance value of each resistor in the resistor area 3 is recorded.
4) The resistive region 3 overlies IMD medium 6.
5) Second metal regions 7 are formed at both ends of the resistive region 3 and connected to the first metal regions 5.
6) A second PCM test is performed and the resistance value of each resistor in the resistor area 3 is recorded.
7) According to the difference value of the resistance values of the same resistor in two PCM tests, the resistance change rate can be calculated, then the resistance change rate is substituted into a specific crystal orientation silicon wafer stress component calculation formula, the stress value introduced to the silicon surface by the IMD dielectric film is calculated, and the stress value of the IMD dielectric film can be obtained according to the force interaction principle.
8) If multiple layers of metal wiring exist, the steps 2) to 7) can be repeated to calculate the stress of the ILD medium introduced to the silicon surface between two adjacent layers of metal areas, the stress introduced to the silicon surface under the combined action of the IMD and the ILD medium, the stress of the passivation film introduced to the silicon surface, the stress introduced to the silicon surface by a thinning process and the stress introduced by a back-metal process.
The semiconductor substrate 1 has a plurality of resistive regions 3 on its surface. The number and layout of resistors in the resistor area designed for calculating the stress are not limited to the schemes shown in fig. 2 and 3, and the doping type may be a combination of N type and P type, or may be any single doping type of N type or P type.
These films may be individually or cumulatively coated on the surfaces of the plurality of resistive regions 3 according to the kind of the film to be monitored for stress. These films may be insulating media or various conductive layers.
The resistance change rate can be calculated according to the difference value of the resistance values of the same resistor in two PCM tests, and is substituted into a specific crystal orientation silicon wafer stress component calculation formula to calculate the film stress introduced between the two PCMs or the silicon surface stress introduced by other process processing.
The resistance region can be replaced by a channel region of the MOS transistor, and stress can be calculated by detecting the resistance of the channel region of the MOS transistor. The nature of the stress represented by the change in resistance of the MOS channel region is the same as the stress represented by the resistive region, and will not be described again.
Example 19:
the method for on-line monitoring the stress introduced into each film layer at the later stage of the control process can calculate the stress value of local positions on the wafer caused by factors such as various dielectric films, metal layers, thinning and the like from the first layer metal wiring to the thinning and back-gold in the stage through multiple PCM tests at different stages, and is beneficial to engineers to know actual stress data and distribution thereof on the product chip and influence of the actual stress data and distribution on the electric performance of devices and circuits. The method has great benefits in process monitoring, process optimization, stress reduction, failure analysis and the like.
The method comprises the following steps:
1) A dielectric masking layer 2 is formed on a semiconductor substrate 1.
2) A plurality of resistor areas 3 arranged according to a certain crystal orientation are formed by adopting an implantation doping or diffusion doping mode and cover the dielectric masking layer 4.
3) First metal regions 5 are formed at both ends of the resistive region 3.
4) A first PCM test was performed.
5) Covering IMD medium 6.
6) Second metal regions 7 are formed at both ends of the resistive region 3 and connected to the first metal regions 5.
7) A second PCM test was performed.
8) The resistance values obtained by the resistive region 3 at the first PCM test and the second PCM test are different due to the influence of the IMD medium 6. The difference in the two tests and the rate of change of resistance are due to the stress introduced by IMD medium 6. From equation (1), it can be seen that the stress sigma accumulated in the resistive region 3 during the second PCM test is performed i ′ j Is the stress sigma accumulated by the first metal region 5 and all the processes preceding it i ′ j Stress Δσ 'introduced with IMD media' ij The common Influence of (IMD) is that the difference between the resistance values obtained by the first and second PCM tests of the same resistor characterizes the stress increment delta sigma 'introduced by the IMD medium' ij (IMD)。
The resistance of a specific layout is designed according to the layout mentioned in the prior literature and is used for testing, and then 6 components delta sigma 'of the stress increment introduced on the silicon surface by the IMD medium on the (111) silicon chip can be calculated' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 13 、Δσ′ 23 、Δσ′ 12 The calculation formula is as follows:
σ′ ij (PCM2)＝σ′ ij (PCM1)+Δσ′ ij (IMD) (1)
or calculating (100) the silicon surface of IMD medium introduction on the silicon chip4 components of stress delta sigma' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 12 The calculation formula is as follows:
9) If multiple layers of metal wiring exist, the steps 2) to 8) can be repeated to calculate the stress of the ILD medium introduced to the silicon surface between two adjacent layers of metal areas, the stress introduced to the silicon surface under the combined action of the IMD and the ILD medium, the stress of the conductive layer introduced to the silicon surface, the stress of the passivation film introduced to the silicon surface, the stress of the thinning process introduced to the silicon surface and the stress introduced by the back gold process.
10 According to the principle of force interaction, if the silicon surface stress is calculated to be compressive, the stress of the corresponding dielectric film is tensile, and vice versa.
Example 20:
a method of on-line monitoring stress by PCM testing, comprising the steps of:
1) Growing an oxide layer on the substrate silicon with the N-type (111) crystal orientation, photoetching, etching a P-type well region, injecting P-type impurities, removing the oxide layer by a wet method, oxidizing at a high temperature and annealing.
2) Photoetching and etching 8 resistor areas, masking PRes 5-PRes 8 by photoresist, injecting N-type impurities into NRes 1-NRes 4 areas, removing photoresist, and positioning NRes 1-NRes 4 in a P-type well area. Wherein the length of the first NRes1 resistor numbered in sequenceThe direction is perpendicular to the main reference plane of the silicon wafer, namely NRes1 is alongAnd (5) crystal orientation. The remaining resistors are placed every 45 deg. interval in a counter-clockwise direction. As shown in fig. 2.
3) Masking NRes 1-NRes 4 with photoresist, injecting P-type impurities into the PRes 5-PRes 8 area, and removing the photoresist. 2) And 3) step (c) is exchangeable.
4) The steps 1), 2) and 3) can be inserted into any semiconductor process using the (111) silicon chip as a carrier, and the impurity activation of the resistor area is combined with the subsequent thermal process of the semiconductor process. The resistor is not required to have a deep junction depth, so the resistor can be selectively placed at the rear stage of the semiconductor process to reduce the influence of process fluctuation on the resistor.
5) After the implantation doping is finished, the processes of first metal wiring, PCM1 test, IMD dielectric deposition, planarization, through hole, second metal wiring, PCM2 test and the like are finished according to the semiconductor process sequence. Tests of 8 resistance values were added and recorded at the time of PCM1 and PCM2 tests. The change rate of the resistance value of the same resistor in two stages of PCM1 and PCM2 corresponds to the stress introduced by the IMD medium. Substituting the corresponding resistance change rate data into six stress components delta sigma 'of the silicon wafer' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 13 、Δσ′ 23 、Δσ′ 12 In the calculation formula of (2), the stress caused by the IMD medium at a specific position on the silicon wafer is calculated.
6) Because the change rate of the resistor under the action of stress is smaller, the change rate of the resistor under the stress of 100MPa is only a few thousandths, and therefore the resistance value of each resistor is considered to be suitable for the stress to be detected. In order to further reduce the error of the resistance, the Kelvin resistance test structure can be designed.
7) If there are a third or more metal wirings after the PCM2, the stress generated by the medium between these metal wirings can be reused 5) to calculate the rate of change of the resistance values before and after the medium coverage and calculate the stress value generated by the corresponding medium on the silicon surface.
Example 21:
a method of on-line monitoring stress by PCM testing, comprising the steps of:
1) Growing an oxide layer on the substrate silicon with the N type (100) crystal orientation, photoetching, etching a P type well region, injecting P type impurities, removing the oxide layer by a wet method, oxidizing at a high temperature and annealing.
2) 4 resistor areas are photoetched and etched, PRes 3-PRes 4 are masked by photoresist, N-type impurities are injected into NRes 1-NRes 2 areas and photoresist is removed, and NRes 1-NRes 2 are located in the P-type well area. Wherein the length direction of the first NRes1 resistor numbered in sequence is required to be perpendicular to the main reference plane of the silicon wafer, namely NRes1 is required to be along [110 ]]And (5) crystal orientation. The NRes2 resistor forms an included angle of 90 degrees with the NRes1 resistor, and the NRes2 resistor is arranged along the direction ofDirection. As shown in fig. 3.
3) PRes3 resistors are placed along the [010] direction and PRes4 resistors are placed along the [100] direction. Masking NRes 1-NRes 2 with photoresist, injecting P-type impurities into PRes 3-PRes 4 areas, and removing the photoresist. 2) And 3) step (c) is exchangeable.
4) The steps 1), 2) and 3) can be inserted into any semiconductor process using the (100) silicon wafer as a carrier, and the impurity activation of the resistor region can be combined with the subsequent thermal process of the semiconductor process. The resistor is not required to have a deep junction depth, so the resistor can be selectively placed at the rear stage of the semiconductor process to reduce the influence of process fluctuation on the resistor.
5) After the implantation doping is finished, the processes of first metal wiring, PCM1 test, IMD dielectric deposition, planarization, through hole, second metal wiring, PCM2 test and the like are finished according to the semiconductor process sequence. Tests of 4 resistance values were added and recorded at the time of PCM1 and PCM2 tests. The change rate of the resistance value of the same resistor in two stages of PCM1 and PCM2 corresponds to the stress introduced by the IMD medium. Substituting the corresponding resistance change rate data into four stress components delta sigma 'of the silicon wafer' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 12 In the calculation formula of (2), the stress caused by the IMD medium at a specific position on the silicon wafer is calculated. The formula of the relation between the resistance change rate and the stress in the silicon wafer only comprises delta sigma' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 12 Four stress components, so the silicon wafer can only solve the four stress components.
6) If there are a third or more metal wirings after the PCM2, the stress generated by the medium between these metal wirings can be reused 5) by calculating the rate of change of the resistance values before and after the medium coverage and calculating the stress value generated by the corresponding medium.
Example 22:
a method of on-line monitoring stress by PCM testing, comprising the steps of:
using the resistors formed in example 20 or example 21, the resistance values of 8 (or 4) resistors were tested and recorded before thinning the silicon wafer
After the silicon wafer is thinned, testing and recording the resistance values of 8 (or 4) resistors, calculating to obtain the change rate of each resistor, and substituting the change rate into six stress component increments delta sigma 'of the silicon wafer' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 13 、Δσ′ 23 、Δσ′ 12 Is substituted into the calculation formula of the four stress component increment delta sigma 'of the silicon wafer' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 12 And (3) calculating the stress increment caused by the thinning process at a specific position on the silicon wafer.
Example 23:
a method of on-line monitoring stress by PCM testing, comprising the steps of:
using the resistors formed in example 20 or example 21, the resistance of 8 (or 4) resistors was tested and recorded before the silicon wafer was back-gold
Testing and recording the resistance values of 8 (or 4) resistors after the silicon wafer is subjected to gold-coating, calculating to obtain the change rate of each resistor, and substituting the change rate into six stress component increments delta sigma 'of the silicon wafer' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 13 、Δσ′ 23 、Δσ′ 12 Is substituted into the calculation formula of the four stress component increment delta sigma 'of the silicon wafer' 11 、Δσ′ 22 、Δσ′ 33 、Δσ′ 12 And (3) calculating the stress increment caused by the back gold process at a specific position on the silicon wafer.

Claims (10)

1. A method for on-line monitoring of stress by PCM testing, comprising the steps of:
1) A plurality of the PCM test regions (3) are formed on a semiconductor substrate (1).
2) And forming an ith metal area (5) at two ends of the PCM test area (3) in the step 1), wherein the initial value of i is 1.
3) Performing an ith PCM test and recording the resistance value of each PCM test area (3);
4) Covering an ith dielectric layer (6) on the PCM test area (3);
5) Forming an (i+1) th metal region (7) at two ends of the PCM test region (3) in the step 4) and connecting with the (i) th metal region (5);
6) Performing an i+1th time of PCM test, and recording the resistance value of each PCM test area (3);
7) Calculating the stress increment of the semiconductor wafer based on the resistance value of each PCM test area (3) in the (i+1) th PCM test and the (i) th PCM test, wherein the stress increment comprises the stress increment introduced into the semiconductor substrate (1) by the (i) th dielectric layer (6);
8) Let i=i+1 and repeat steps 2) to 7), the semiconductor wafer stress increase that occurs after each metal region formation is measured until the semiconductor device fabrication is completed.
2. A method of on-line monitoring of stress by PCM testing according to claim 1, characterized in that the PCM test zone (3) comprises a resistive zone or a MOS transistor channel zone.
3. A method of on-line monitoring of stress by PCM testing according to claim 1, wherein the means of forming a plurality of PCM test regions (3) comprises implantation doping means, diffusion doping means, doping types comprising: n-type, P-type, a combination of N-type and P-type.
4. A method of on-line monitoring of stress by PCM testing according to claim 1, characterized in that the i-th dielectric layer (6) comprises an IMD dielectric layer, an ILD dielectric layer, an isolated metal layer, a passivation film layer.
5. A method of on-line monitoring of stress by PCM testing according to claim 1, wherein the semiconductor wafer stress delta further comprises a stress delta introduced to the semiconductor substrate (1) when the 1 st dielectric layer, …, the i-th dielectric layer co-act when i is equal to or greater than 2.
6. Method for in-line monitoring of stress by PCM testing according to claim 1, characterized in that when a thinning process is involved in the fabrication of a semiconductor chip from a semiconductor substrate (1), the following steps are also performed:
s 1) performing a jth PCM test and recording the resistance value of each PCM test zone (3);
s 2) performing a thinning process;
s 3) performing a j+1th PCM test and recording the resistance value of each PCM test zone (3);
s 4) calculating the stress increment introduced to the semiconductor substrate (1) by the thinning process based on the resistance value of each PCM test area (3) in the j+1th and j th PCM tests.
7. Method for in-line monitoring of stress by PCM testing according to claim 1, characterized in that when a back gold process is involved in the fabrication of a semiconductor chip from a semiconductor substrate (1), the following steps are also performed:
s 1) performing a kth PCM test and recording the resistance value of each PCM test zone (3);
s 2) executing a gold backing process;
s 3) performing a (k+1) th PCM test and recording the resistance value of each PCM test zone (3);
s 4) calculating the stress increment introduced to the semiconductor substrate (1) by the back-gold process based on the resistance value of each PCM test zone (3) in the k+1th and k-th PCM tests.
8. A method of on-line monitoring of stress by PCM testing according to claim 1, characterized in that the delta of stress introduced to the semiconductor substrate (1) by the ith dielectric layer (6) is characterized by the difference in resistance of the same PCM test zone (3) at the i+1th PCM test and the i-th PCM test.
9. A method of on-line monitoring of stress by PCM testing according to claim 1, wherein the semiconductor wafer stress further comprises the stress delta experienced by the i-th dielectric layer (6) itself.
10. A method for on-line monitoring of stress by PCM testing according to claim 9, wherein the calculation of the stress of the i-th dielectric layer (6) itself comprises: and taking the negative of the stress increment value introduced into the semiconductor substrate (1) by the ith dielectric layer (6) based on the force interaction principle to obtain the stress increment received by the ith dielectric layer (6) per se.
CN202310709688.XA 2023-06-15 2023-06-15 Method for online monitoring stress through PCM (pulse code modulation) test Pending CN116895548A (en)

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