JP2010186775A - Crystal defect detection element for monitor, semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a crystal defect detection element for a monitor capable of detecting the crystal defect of a silicon substrate generated by the influence of a process with high sensitivity, a semiconductor device and a method of manufacturing it. <P>SOLUTION: The crystal defect detection element for the monitor includes an element isolation film 11 formed on the silicon substrate and a plurality of transistors formed in an element region 10c on the inner side of the element isolation film 11. The gate electrodes 12 of the plurality of transistors respectively are electrically connected to each other, the diffusion layers 10a of the source regions of the plurality of transistors respectively are electrically connected to each other, and the diffusion layers 10b of the drain regions of the plurality of transistors respectively are electrically connected to each other. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a crystal defect detecting element for monitoring, a semiconductor device, a manufacturing method thereof, and the like, and in particular, a crystal defect detecting element for monitoring, a semiconductor device, and a manufacturing thereof that can detect a crystal defect of a silicon substrate caused by the influence of a process with high sensitivity. Regarding the method.

  Examples of the semiconductor wafer include a silicon substrate and an SOI (Silicon on Insulator) substrate. Semiconductor devices are formed on these semiconductor wafers. Further, miniaturization, high integration, high speed and high yield are required for semiconductor devices. Also, the performance and yield of semiconductor devices are greatly affected by the quality of the semiconductor wafer. In the quality of the semiconductor wafer, the quality of the oxide film formed by thermally oxidizing the semiconductor wafer reflects the quality of the oxide film formation conditions, the crystal quality of the surface portion of the semiconductor wafer, and the like.

  In the manufacturing process of a semiconductor device, crystal defects are generated in the silicon substrate due to stress strain caused by the difference in thermal expansion coefficient between the diffusion region and the element isolation insulating film in the thermal process. Due to the generated crystal defects, there is a problem that the characteristics of the semiconductor element formed on the silicon substrate deteriorates and the junction leakage current of the semiconductor element increases. Therefore, in order to suppress the generation of crystal defects, it is an important issue to evaluate the crystal defects in the silicon substrate.

FIG. 6 is a plan view showing a TEG (Test Element Group) structure for measuring off-leakage of a single transistor.
As shown in FIG. 6, an element isolation film 11 is formed on a silicon substrate by, for example, an STI (Shallow Trench Isolation) method. Next, the gate electrode 12 having the gate length L of about 0.14 μm, the diffusion layers 10a and 10b in the source / drain regions, and the sub-contact 14 are formed on the silicon substrate.

  As a technique for evaluating crystal defects, generally, a terminal is provided in an evaluation pattern of a diffusion region formed on a silicon substrate as shown in FIG. 6, and a junction leakage current of a semiconductor element constituted by the evaluation pattern is detected. There is a technique.

  However, if a random crystal defect of a silicon substrate caused by the influence of a process such as STI stress is detected by detecting an off-leakage current of a single transistor having a small area shown in FIG. Since the off-leakage current value of the transistor is extremely small, the current value that can be detected by the prober becomes larger and cannot be detected. For this reason, the product has been confirmed by hot spot analysis or IQ value (see, for example, Patent Document 1).

JP 2004-311700 A

  As described above, the method of detecting the off-leakage current of a single transistor cannot detect crystal defects with high sensitivity. In addition, the detection of crystal defects in the silicon substrate by the hot spot analysis described above has a problem that analysis time and advanced technology are required. In addition, in the above-described IQ value measurement of a semiconductor product, it is necessary to stack a plurality of metal films for product confirmation, and there is a problem that it takes time to manufacture a sample.

  Further, as described above, in a normal resolution prober, the detectable current value is larger than the off-leak current of a single transistor. Therefore, when the off-leakage of the transistor is very small, the off-leakage cannot be measured unless the prober has a high resolution. Therefore, when a prober with high resolution is used, the cost of detecting crystal defects increases.

  The present invention has been made in consideration of the above, and an aspect according to the present invention is a crystal defect detecting element for monitoring, a semiconductor device, and a semiconductor device capable of detecting a crystal defect of a silicon substrate caused by the influence of a process with high sensitivity. The manufacturing method thereof.

In order to solve the above problems, a crystal defect detecting element for monitoring according to the present invention includes an element isolation film formed on a silicon substrate,
A plurality of transistors formed in an element region inside the element isolation film;
A crystal defect detecting element for monitoring, comprising:
The gate electrodes of the plurality of transistors are electrically connected to each other;
A diffusion layer of a source region of each of the plurality of transistors is electrically connected to each other;
The diffusion layers in the drain regions of the plurality of transistors are electrically connected to each other.

  The monitoring crystal defect detecting element has a plurality of transistors formed in the element region inside the element isolation film. Thereby, the crystal defect of the silicon substrate can be detected with higher sensitivity than in the case where the single transistor is a crystal defect detection element for monitoring.

  In the monitoring crystal defect detecting element according to the present invention, the plurality of transistors are preferably 100 or more transistors, and the element isolation film is preferably STI.

  In the monitoring crystal defect detection element according to the present invention, the plurality of transistors may be configured such that the diffusion layers in the source region and the diffusion layers in the drain region are alternately adjacent to each other, The gate electrode is preferably disposed between the drain region and the diffusion layer.

  In the crystal defect detecting element for monitoring according to the present invention, it is preferable that the plurality of transistors are arranged in a matrix.

  Further, in the semiconductor device according to the present invention, the described crystal defect detecting element for monitoring can be arranged on a scribe line of a semiconductor wafer.

  Further, in the semiconductor device according to the present invention, it is also possible to perform off-leak measurement by arranging the described crystal defect detecting element for monitoring on a scribe line of a semiconductor wafer.

The enlarged view of the TEG structure concerning the embodiment of the present invention. The TEG structure which concerns on embodiment of this invention. Sectional drawing of the AA 'part shown in FIG. The graph which shows an off-leak measurement result. The graph which shows an off-leak measurement result. Conventional TEG structure for measuring off-leakage of a single transistor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 and 2 are plan views for explaining a TEG structure (a crystal defect detecting element for monitoring) for measuring off-leakage of a transistor according to an embodiment of the present invention. FIG. 1 is a diagram showing the TEG shown in FIG. It is the figure which expanded a part of structure. FIG. 3 is a cross-sectional view taken along line AA ′ shown in FIG. 2 and is a cross-sectional view for explaining a method for manufacturing the TEG.

  The TEG structure shown in FIGS. 1 and 2 includes a diffusion layer 10a in the source region, a diffusion layer 10b in the drain region, a gate electrode 12, and a subcontact region 14, and a plurality of transistors (100 or more are preferable) in parallel. Arranged and connected. The sub-contact region 14 is a region for applying a potential to the silicon substrate.

  A diffusion region 10c shown in FIG. 1 is a region in which five diffusion layers 10a and 10b are adjacent to each other through a gate electrode 12, and four transistors are formed in this region. A plurality of diffusion regions 10c are arranged in a matrix as shown in FIG. Spaces S are respectively provided between the horizontally adjacent diffusion regions 10c and between the vertically adjacent diffusion regions 10c in FIG.

Hereinafter, the TEG structure will be described in detail.
As shown in FIG. 1, in the diffusion region 10c, a source region diffusion layer 10a, a drain region diffusion layer 10b, a source region diffusion layer 10a, a drain region diffusion layer 10b, and a source region diffusion layer 10a are formed. A gate electrode 12 is disposed between the diffusion layers 10a and 10b. The four gate electrodes 12 and the diffusion region 10c are set as one set, and this set is repeatedly arranged as shown in FIG.

  As shown in FIGS. 2 and 1, the diffusion layers 10a in all the source regions are electrically connected to the metal wiring 13a through the plug 15, and this metal wiring 13a is electrically connected to the source terminal (not shown). Connected. Accordingly, the diffusion layers 10a of all the source regions are in a state of being electrically connected to each other. Further, the diffusion layers 10b in all the drain regions are electrically connected to the metal wiring 13b through the plug 15, and the metal wiring 13b is electrically connected to a drain terminal (not shown). Accordingly, the diffusion layers 10b in all the drain regions are electrically connected to each other. All the gate electrodes 12 are electrically connected to the metal wiring 13c through the plug 15, and the metal wiring 13c is electrically connected to a gate terminal (not shown). Accordingly, all the gate electrodes 12 are electrically connected to each other.

Next, a method for manufacturing the TEG will be described.
First, as shown in FIG. 3, an element isolation film 11 is formed on a silicon substrate 1 by, for example, an STI (Shallow Trench Isolation) method. Next, a gate oxide film to be the gate insulating film 2 is formed by a thermal oxidation method. Thereafter, a gate electrode 12 is formed by processing a polysilicon film formed on the gate insulating film 2 by a CVD (Chemical Vapor Deposition) method using a photolithography method and a dry etching method.

  Next, impurity ions are ion-implanted into the silicon substrate 1 using the gate electrode 12 and the element isolation film 11 as a mask, and a heat treatment is performed to form a diffusion layer 10a in the source region and a diffusion layer 10b in the drain region.

  Next, the interlayer insulating film 3 is formed on the entire surface of the substrate including the gate electrode 12, the source region diffusion layer 10a and the drain region diffusion layer 10b by the CVD method. Next, a plug 15 is formed by embedding a metal film (for example, a W film) in the interlayer insulating film 3. Thereafter, metal wires (for example, Al alloy wires) 13 a to 13 c are formed on the plug 15 and the interlayer insulating film 3. As a result, the diffusion layers 10a in all the source regions are electrically connected to the metal wiring 13a via the plug 15, and the diffusion layers 10b in all the drain regions are electrically connected to the metal wiring 13b via the plug 15. All the gate electrodes 12 are electrically connected to the metal wiring 13c through the plug 15 shown in FIG.

  As described above, according to the embodiment of the present invention, a plurality of transistors adjacent to the diffusion region 10c are formed, and a plurality of the diffusion regions 10c are arranged in a matrix, thereby providing a crystal defect detecting element for monitoring having 100 or more transistors. Is configured. In this crystal defect detecting element for monitoring, all gate electrodes 12 are electrically connected to each other, diffusion layers 10a in all source regions are electrically connected to each other, and diffusion layers 10b in all drain regions are electrically connected to each other. 100 or more transistors are connected in parallel. For this reason, the crystal defect of the silicon substrate can be detected with higher sensitivity than when the single transistor is a crystal defect detection element for monitoring.

  More specifically, when the off-leakage current of a transistor is measured using a monitoring crystal defect detecting element composed of a single transistor, the off-leakage current value becomes smaller than the detection limit of the prober. On the other hand, a predetermined potential is applied to the gate terminal, the source terminal, the drain terminal, and the sub-contact region of the monitoring crystal defect detecting element in which 100 or more transistors are connected in parallel as in this embodiment, so that the off-leak current of the transistor , The off-leakage current value is 100 times or more that of a single transistor. Therefore, the crystal defect of the silicon substrate can be detected with higher sensitivity than when the single transistor is a crystal defect detection element for monitoring. That is, even a prober with a low resolution can detect a minute off-leakage of a transistor and can easily detect a crystal defect of a silicon substrate.

  Further, in this embodiment, the arrangement interval of each transistor is narrowed, that is, a plurality of transistors are formed in the diffusion region 10c, and the space S that is the mutual interval between the plurality of diffusion regions 10c arranged in a matrix is reduced. By doing so, it is possible to detect a highly sensitive crystal defect by measuring the off-leakage current of the transistor. The reason for this is that as the arrangement interval of a plurality of transistors is narrowed, the influence of STI stress increases and it becomes easier to detect crystal defects.

  Further, it is possible to detect a crystal defect of a silicon substrate with high sensitivity without performing hot spot analysis that requires analysis time and high technology, and measuring an IQ value of a semiconductor product that requires time for sample preparation.

  FIG. 4 is a graph showing the results of measuring off-leakage using the sample of the TEG structure shown in FIGS. The number of transistors in each sample is 1437, and the off-leakage value shown in FIG. 4 is a value per transistor divided by 1437. Further, the gate length L of the transistor of each sample is 0.14 μm, and the gate width W of the transistor is 5 μm. Samples are prepared by changing the space S shown in FIG. 1 to 0.22 μm, 0.26 μm, 0.5 μm, and 1.0 μm, respectively, and arsenic (Arsenic) ions are added to the source / drain diffusion layers 10a and 10b. And phosphorus (Phosphorus) ions were separately prepared and ion-implanted samples were prepared. In addition, 30 samples were prepared.

  Each of the gate electrode 12, the sub-contact 14, and the diffusion layer 10a in the source region was connected to the ground potential, and an off-leak measurement was performed by applying a voltage to the diffusion layer 10b in the drain region.

  As shown in FIG. 4, when arsenic ions are implanted, the off-leak value is increased by narrowing the space S. This is because, when the space S is narrowed, the formation region of the element isolation film 11 is also narrowed, and the influence of thermal expansion (STI stress) in the process of the element isolation film 11 increases, resulting in crystal defects in the silicon substrate. This means that it becomes easier to detect the generated crystal defects. In other words, it can be said that it is preferable to narrow the space S when producing a crystal defect detecting element for monitoring.

  In addition, as shown in FIG. 4, the sample into which phosphorus ions are implanted has a low off-leak value regardless of the size of the space S. This means that no crystal defects were detected in the sample into which phosphorus ions were implanted. In other words, arsenic ions, which are heavier than phosphorous ions, tend to form crystal defects in the silicon substrate, which means that the formed crystal defects were detected, and there were crystal defects compared to the arsenic ion sample. The result was that no crystal defects were detected in the sample of phosphorus ions that were difficult to form.

  According to FIG. 4, in the case of a single transistor, when the off-leakage of the transistor is measured, 1 pA, which is the detection limit of the prober, becomes a measured value. However, by measuring a plurality of transistors such as 1437, it can be seen that the off-leakage of one transistor is 0.05 pA. That is, it becomes possible to accurately measure the off-leak value of a single transistor even with a low-resolution prober.

  FIG. 5 is a graph showing the results of measuring off-leakage using the samples having the TEG structure shown in FIGS. The number of transistors in each sample is 1437, and the off-leak value shown in FIG. 5 is a value per transistor divided by 1437. Further, the gate length L of the transistor of each sample is 0.14 μm, and the gate width W of the transistor is 0.5 μm. Samples are prepared by changing the space S shown in FIG. 1 to 0.22 μm, 0.26 μm, 0.5 μm, and 1.0 μm, respectively, and arsenic (Arsenic) ions are added to the source / drain diffusion layers 10a and 10b. And phosphorus (Phosphorus) ions were separately prepared and ion-implanted samples were prepared.

  Each of the gate electrode 12, the sub-contact 14, and the diffusion layer 10a in the source region was connected to the ground potential, and an off-leak measurement was performed by applying a voltage to the diffusion layer 10b in the drain region.

  As shown in FIG. 5, when the gate width W of the transistor was made smaller than that in FIG. 4, the off-leakage value did not increase even when the space S was narrowed, and no crystal defects were detected. This means that it is easier to detect crystal defects when the gate width W of the transistor is increased, and it can be said that the detection sensitivity of crystal defects can be increased when the gate width W is increased. Further, if the gate width W is 1 μm or more, it is effective in improving the detection sensitivity of crystal defects.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the crystal defect detecting element for monitoring according to the above embodiment may be arranged on a scribe line of a semiconductor wafer to check the influence of STI stress in the wafer manufacturing process, or the influence of STI stress when designing the wafer manufacturing process. In order to confirm this, the crystal defect detecting element for monitoring according to the above embodiment may be used.

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Gate insulating film, 3 ... Interlayer insulating film, 11 ... Element isolation film, 12 ... Gate electrode, 10a ... Diffusion layer of source region, 10b. ..Diffusion layer in drain region, 10c ... Diffusion region, 14 ... Sub-contact, 15 ... Plug, 13a, 13b, 13c ... Metal wiring

Claims (6)

An element isolation film formed on a silicon substrate;
A plurality of transistors formed in an element region inside the element isolation film;
A crystal defect detecting element for monitoring, comprising:
The gate electrodes of the plurality of transistors are electrically connected to each other;
A diffusion layer of a source region of each of the plurality of transistors is electrically connected to each other;
A monitoring crystal defect detecting element, wherein diffusion layers in drain regions of the plurality of transistors are electrically connected to each other.   2. The crystal defect detecting element for monitoring according to claim 1, wherein the plurality of transistors are 100 or more transistors, and the element isolation film is STI.   3. The plurality of transistors according to claim 1, wherein the source region diffusion layer and the drain region diffusion layer are alternately adjacent to each other, and the source region diffusion layer and the drain region diffusion layer A monitoring crystal defect detecting element, wherein the gate electrode is disposed between each other.   A crystal defect detecting element for monitoring, wherein the plurality of transistors according to claim 3 are arranged in a matrix.   5. A semiconductor device, wherein the monitoring crystal defect detecting element according to claim 1 is disposed on a scribe line of a semiconductor wafer.   A method for manufacturing a semiconductor device, comprising: disposing a crystal defect detecting element for monitoring according to claim 1 on a scribe line of a semiconductor wafer and performing off-leakage measurement.

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