JPH01265532A - Pattern for evaluation of interlayer insulating film - Google Patents

Abstract

PURPOSE:To evaluate the flow angle of an interlayer insulating film by a method wherein the interlayer insulating film is evaluated by measuring the continuity of wiring patterns using evaluation patterns provided with lower layer patterns and wiring patterns formed to traverse the lower layer patterns through the interlayer insulating film. CONSTITUTION:An interlayer insulating film such as PSG film or BPSG film, etc., is formed on a polysilicon pattern 4. Six metal wirings 5a-5g traversing the polysilicon pattern 4 are formed on the interlayer insulating film. The shortcircuit between the wirings 5a and 5b or between the wirings 5b and 5c in the region A can be detected by measuring the conductivity between a pad 6 and a pad 7b. Likewise, the shortcircuit between the wirings 5c and 5d or between the wirings 5d and 5e in the region B can be detected by measuring the continuity between the pad 6 and a pad 7a. Through these procedures, the flow angle of the interlayer insulating film can be evaluated.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a pattern for evaluating a device structure in a semiconductor integrated circuit device manufacturing line, and in particular evaluates the flow angle of an interlayer insulating film, and based on the flow angle of an interlayer insulating film. The present invention relates to an evaluation pattern for managing the occurrence of defects in a wiring pattern due to unevenness of an insulating film.

(Conventional technology) FIG. 3 shows an example of the wiring structure.

Reference numeral 1 denotes a lower pattern made of a polysilicon layer, on which an interlayer insulating film 2 is formed, and on the interlayer insulating film 2, a metal wiring 3 is formed.

Irregularities occur on the surface of interlayer insulating film 2 due to the steps of polysilicon pattern 1 . The size of the unevenness is determined by the interlayer insulating film 2.
can be expressed as the flow angle θ. The flow angle θ largely depends on the space between adjacent patterns of the polysilicon pattern l, which is the underlying pattern, and in boat fishing, the flow angle θ becomes critical when the space becomes less than a certain size.

When the flow angle θ becomes urgent, the interlayer insulating film 2
When forming a metal film on top and patterning it by photolithography and etching to form the metal wiring 3, the metal layer may remain between the metal wirings 3 and cause a short circuit, or the metal wiring 3 may be disconnected at a stepped portion. defects occur.

Conventionally, in order to evaluate the flow angle θ of the interlayer insulating film 2, a method of directly observing I2 of the target sample, such as performing SEMwt observation of a cross section of the interlayer insulating film 2, has been adopted. However, in that case, observation cannot be made unless the target sample is destroyed. Therefore, such a method is inappropriate for managing a production line.

In order to nondestructively control the interlayer M edge film 2 on the manufacturing line, it is necessary to rely on indirect methods such as controlling the impurity concentration of the PSG film, BPSG film, etc. used for the interlayer insulating film 2. do not have. The surface of these interlayer #4A edge films is smoothed by heat treatment after deposition, and the flow angle θ
This is because it depends on the impurity concentration.

(Objective) An object of the present invention is to enable the flow angle of an interlayer insulating film to be evaluated by electrical measurement, and to enable wiring defects to be managed based on the evaluation results.

(Structure) The present invention includes a lower layer pattern formed on a mass production wafer and designed according to rules stricter than device design rules, and a wiring pattern formed across the lower layer pattern via an interlayer MA edge film. This is a pattern in which the interlayer insulating film is evaluated based on the rule of the lower layer pattern in a portion where a defect has occurred through conduction measurement of the wiring pattern.

This evaluation pattern is formed on another wafer in advance.

The flow angle θ of the interlayer insulating film at the portion where the wiring pattern has a defect is measured by SEM observation or the like.

Next, this evaluation pattern is formed on a mass production wafer, and based on the rules of the lower layer pattern of the part where the wiring pattern has a defect, the wiring pattern is be able to control whether defects occur.

Examples will be specifically described below.

FIG. 1 represents one embodiment.

A pattern 4 indicated by a broken line is a polysilicon pattern which is a lower layer pattern, and is formed in three regions A, B, and C. The space between polysilicon patterns 4 is 1.0 μm in area A.

In region B, it is 1.2 μm, and in region C, it is 1.4 μm. Both of these spaces are stricter than the device design rules (for example, 2 μm).

An interlayer insulating film such as a PSG film or a BPSG film is formed on the polysilicon pattern 4. Six metal interconnections 5a to 5g are formed across the polysilicon pattern 4 on the interlayer #@edge film. These metal wiring 5
8-5g are parallel to each other and the spacing is 2 μm.

Metal wirings 5a, 5c, 5e, and 5g are all connected to pad 6, metal wiring 5b is connected to pad 7b, metal wiring 5d is connected to pad 7a, and metal wiring 5f is connected to pad 7b.
is connected to pad 7c.

The space between metal wiring 5a and metal wiring 5b and the space between metal wiring 415b and metal wiring 5c are in area A, and the space between metal wiring 5c and metal wiring #I5d and the space between metal wiring 5d and metal wiring 5e are in area A. The space between is in area B, where metal wiring 5e and metal wiring 5f
The space between them and the space between the metal wiring 5f and the metal wiring 5g are in region C.

By measuring the conductivity between pad 6 and pad 7b, it is possible to detect a short circuit between wiring patterns 5a and 5b in area A or a short circuit between wiring patterns 5b and 50. By measuring the conduction between pads 6 and 7c, it is possible to detect a short circuit between wiring patterns 5c and 5d or between wiring patterns 5d and 5e in region B, and by measuring conduction between pads 6 and 7c. By this, wiring patterns 5e and 5b in area C
A short circuit between the wiring patterns 5f and 5g or a short circuit between the wiring patterns 5f and 5g can be detected.

This evaluation pattern is formed on a wafer, and the conductivity between pad 6 and pads 7a, 7b, and 7c is measured to find the polysilicon pattern space where wiring short circuits begin to occur in various interlayer insulating films.

The measurement results are shown in FIG. D is the case where the spacing of the upper layer metal pattern is 2 μm, and E is the case where the space is 1 μm. The flow angle O was determined by SEM observation of the interlayer insulating film at that portion.

Next, this evaluation pattern is formed on a portion of a mass-produced wafer, for example, on a scribe line, together with mass-produced chips in a mass-produced manufacturing process.

Then, by measuring the continuity between pad 6 and pads 7a, 7b, and 7c, the space in polysilicon pattern 4 where wiring short circuits begin to occur is determined. the.

Applying the obtained space of the polysilicon pattern 4 to the measurement results in Fig. 2, if the space between the wiring patterns 58 to 5g is 2 μm, use p, and if the space between the wiring patterns 58 to 5g is 1 μm, use E to determine the interlayer insulating film. Find the flow angle O.

(Effects) The present invention uses an evaluation pattern that includes a lower layer pattern designed according to rules stricter than the device design rules, and a wiring pattern Y formed across the lower layer pattern via an interlayer insulating film. Since the interlayer insulating film is evaluated by measuring the conductivity of the wiring pattern, the interlayer I! is a non-destructive measurement. ! Membrane flow angle can be assessed. Since this evaluation method is simple, it becomes possible to manage defects in wiring patterns on the production line.

[Brief explanation of the drawing]

Figure 1 is a plan view showing one embodiment, and Figure 2 is a polysilicon pattern space and flow angle of 0 in one embodiment.
FIG. 3 is a cross-sectional view showing general wiring. 4...Polysilicon pattern, 58~5g...
...Metal wiring pattern.

Claims (1)

[Claims] (1) A lower layer pattern formed on a mass production wafer and designed according to rules stricter than device design rules, and a wiring pattern formed to cross the lower layer pattern via an interlayer insulating film, and the wiring pattern A pattern in which the interlayer insulating film is evaluated based on the rules of the lower layer pattern in a portion where a defect has occurred through continuity measurement.