JPH053237A - Method of detecting misalignment between through-hole and upper layer wiring - Google Patents

Abstract

PURPOSE:To provide a detection pattern which facilitates reduction of an inspection time and can cope with the high density of multilayer interconnection. CONSTITUTION:A detection pattern which is formed on a semiconductor substrate 5 together with a semiconductor device in order to detect the misalignment between the through-holes and the upper layer wiring of the semiconductor device is composed of a lower layer pattern 10 which is extended along a direction of discrepancy detection, a detecting through-hole 20 which is so formed as to cross over the lower layer pattern 10 and an upper layer pattern 30 which is so formed as to cover the detecting through-hole 20 and cross over the lower layer pattern 10. After a photolithography process is finished, the resistance value of the lower layer pattern 10 between predetermined points located on both the sides of the detecting through-hole 20 is measured. By the resistance measurement, the defect of the semiconductor device caused by over-etching can be detected indirectly. Thus, an inspection time can be reduced by electrical measurement and, further, alignment margin against the high density of multilayer interconnection can be evaluated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a detection pattern formed in a vacant region or the like when manufacturing a semiconductor device using a multi-layer wiring technique, and through holes and upper layer wiring in a photolithography process in the semiconductor device. The present invention relates to a through hole / upper layer wiring misalignment detection method for detecting misalignment with.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there is one as shown in FIG. The configuration will be described below with reference to the drawings.

FIG. 2 is a diagram showing an example of a conventional detection pattern for measuring misalignment between a through hole and an upper layer wiring.

This detection pattern is an example of a vernier pattern formed in the empty area at the same time as the lower layer wiring which is the circuit pattern in the semiconductor device, the interlayer insulating film in which the through holes are formed, and the upper layer wiring.
It is composed of a scale-patterned through-hole pattern (shown by a broken line in the figure) 1 formed in the through-hole process, and a scale-patterned upper-layer pattern (shown by a solid line in the figure) 2 formed in a subsequent upper-layer wiring forming process. ing. The guide pattern 3 is formed along the vernier formed by the through hole pattern 1 and the upper layer pattern 2. The guide pattern 3 has instruction symbols 3b and 3c transferred from the center point 3a thereof in the plus (+) direction and the minus (-) direction, respectively. In this figure, the scale pitch P1 of the through-hole pattern 1 is 1 μm, and the scale pitch P2 of the upper layer pattern 2 is 0.9 μm.

In FIG. 2, the center point 3a of the guide pattern 3 is shown.
The through-hole pattern 1 and the upper layer pattern 2 coincide with each other on the first scale in the plus direction. Therefore, this is an example of a pattern in the case where a deviation of 0.1 μm occurs in the plus direction, and by using such a vernier, it is possible to determine at what scale the through-hole pattern 1 and the upper layer pattern 2 match. By inspecting by using, it is possible to measure the amount of misalignment between the through hole and the upper wiring in the photolithography process in the semiconductor device.

Incidentally, in FIG. 2, two points in the plus (+) direction and the minus (-) direction from the center point 3a of the guide pattern 3 are shown.
The amount of deviation can be measured in the direction of detection, but such a detection pattern can be formed in a cross shape by changing the direction by 90 degrees,
By forming each in the orthogonal empty regions, it is possible to measure the deviation amount in the four detection directions.

[0007]

However, the misalignment detection method using the detection pattern according to the prior art described above has the following problems.

(1) Since the measurement of the misalignment amount by the vernier is performed by the operator using an optical microscope or the like, this inspection / measurement requires a long time. Currently, several tens to several hundreds of semiconductor devices are formed at one time on a 5-inch or 6-inch silicon wafer.
The mask alignment in the photolithography used in each step is performed for each pattern of the semiconductor device by the die-by-die method. Therefore, the direction and amount of misalignment in each semiconductor device are different.
Therefore, if there are tens of semiconductor devices to be inspected on one silicon wafer, the number of products in the product lot may be several thousand, and if each of these is inspected using an optical microscope or the like, A great deal of time is required, and the inspection process becomes a bottleneck, reducing productivity. Thus, it is impossible and difficult to judge and inspect the deviation amount in all semiconductor devices by operator's visual observation, and there is a problem that it is not practical for quality inspection and management of semiconductor device products.

(2) In recent years, in semiconductor devices, multilayer wiring has come to be frequently used as the functions thereof have become sophisticated and complicated. Multilayer wiring is wiring in which a wiring conductor and an interlayer insulating film having a through hole are sequentially laminated to have a plurality of conductor layers, and the constituent elements are mutually connected through the through hole. It has one circuit function. This is especially true in logic circuit semiconductor devices, where CAD
It is an indispensable technique for increasing the degree of freedom of wiring layout in consideration of automatic wiring by (Computer Aided Design).

As a method of improving the wiring density (integration degree) of the multi-layer wiring, firstly, there is a reduction of the wiring width and spacing, and secondly there is a reduction of the alignment margin. The alignment margin is an allowance for the upper layer pattern in the semiconductor manufacturing process in consideration of the alignment accuracy of the photolithography process between the pattern of a certain layer and the pattern of the layer above it. The alignment margin between the hole and the upper layer wiring becomes a problem. Now, it is desired to reduce this alignment margin. Figure 3
The actual benefits of reducing the alignment margin will be explained using.

FIG. 3 is a diagram showing two conventional wiring configuration examples having different alignment margins d and showing the relationship between the alignment margin d and the wiring pitches P3 and P4.

3 (a) and 3 (b) show the diameter w of the through holes 1-1 and 1-2 and the second layer wirings 2-1 and 2-2, respectively.
-2 has the same minimum wiring width L and minimum wiring interval t, and the through holes 1-1 and 1-2 and the second layer wirings 2-1 and 2-2
The pitches of the second-layer wirings are shown with the alignment margins d1 and d2 of 0.6 μm and 0.3 μm, respectively.

As shown in FIG. 3A, the through hole 1
-1 and the second layer wiring 2-1 have an alignment margin d1 of 0.6 μ.
m, the pitch P3 of the second layer wiring 2-1 is 3.
Although it is 4 μm, as shown in FIG. 3B, when the alignment margin d2 is 0.3 μm, the pitch P4 is 2.8 μm. In this way, the pitch of the second layer wiring can be reduced by twice as much as the reduction of the alignment margin d.

However, the detection pattern using the vernier as shown in FIG. 2 is formed in a vacant region of the semiconductor device simply for measuring the misalignment amount, and a defect in manufacturing the semiconductor device (for example, It has nothing to do with disconnection). For example, if mask alignment is performed in the photolithography process, exposure and development are performed, and then etching is performed, if there is a misalignment between the through hole and the upper layer wiring, the lower layer wiring may be overetched and disconnected. The semiconductor device causes some trouble when misalignment more than an allowable amount occurs in the manufacturing process. However, the detection pattern using the vernier cannot be expressed even until such a judgment as to whether the misalignment amount is an allowable amount or not, and it is only revealed by visual measurement.

Further, even if the semiconductor device product itself is inspected by a resistance measuring instrument or the like, if it is not an initial defect such as reliability deterioration, it is difficult to pass the inspection and find out. Therefore, the detection method using the detection pattern using the vernier is not satisfactory in terms of technology and content in increasing the density of the multilayer wiring.

The present invention has the problems that it takes a long time to inspect the product by measuring the amount of misalignment, and that the detection pattern by the vernier cannot indicate the defect of the product, and the present invention has a problem in the multilayer wiring. It is intended to provide a method for detecting misalignment of through-holes / upper layer wiring, which solves the problem that it is irrelevant to high density.

[0017]

In order to solve the above-mentioned problems, the present invention provides a lower wiring on a semiconductor substrate, an interlayer insulating film having a through hole formed therein, and the lower wiring via the through hole. When manufacturing a semiconductor device in which an upper layer wiring connected to the above is sequentially laminated, a through hole for detecting misalignment between the through hole and the upper layer wiring is used by using a detection pattern provided in an empty area of the semiconductor device. In the upper layer wiring misalignment detection method, the detection pattern is configured as follows.

That is, the detection pattern includes a lower layer pattern which is disposed between the semiconductor substrate and the interlayer insulating film when the lower layer wiring is formed, and which extends in the misalignment detection direction with a predetermined wiring width, and the lower layer pattern. The detection through-hole which is opened in the interlayer insulating film so as to be wider than the wiring width and the detection with the same alignment margin as the detection displacement to be detected at the position corresponding to the alignment detection direction. And an upper layer pattern intersecting the lower layer pattern so as to cover the through hole for use.

Then, using this detection pattern, the resistance value between predetermined portions on both sides of the detection through hole in the lower layer pattern is measured, and the misalignment between the through hole and the upper layer wiring is based on the resistance value. Is to detect.

[0020]

Since the present invention has constituted the method for detecting the misalignment of the through hole / upper layer wiring as described above, the measurement by the detection pattern appears to be related to the etching state in the photolithography process. .. When the amount of detection deviation to be detected exceeds the alignment allowance, the detection pattern acts to cause a misalignment of the through hole of the semiconductor device and the upper layer wiring that is equal to or more than an allowable value, and to disconnect the lower layer pattern. This can be regarded as emphasizing the defects that occur in the semiconductor device.Therefore, by measuring the resistance value between the predetermined positions on both sides of the detection through hole in the lower layer pattern of the detection pattern, the misalignment can be measured by an automatic measuring instrument or the like. It becomes possible to detect it with a dynamic measurement. As a result, the occurrence of misalignment exceeding the alignment margin is indirectly matched as a disconnection phenomenon even in the semiconductor device, so that simple measurement can be performed without using a manual inspection device such as an optical microscope. Further, since it is possible to judge whether or not the amount of misalignment is an allowable amount, it can be used for evaluation of the misalignment allowance in increasing the density of the multilayer wiring. Therefore, the above problem can be solved.

[0021]

FIG. 1 is a schematic plan view of a detection pattern used in an embodiment of the present invention.

This detection pattern is for detecting misalignment in the direction of the arrow in FIG. 1 (deviation detection direction),
The lower layer pattern 10, the detection through hole 20 formed in the interlayer insulating film, and the upper layer pattern 30 are formed on the semiconductor substrate 5. Semiconductor device
Several tens are formed on a semiconductor substrate 5 such as a silicon wafer by, for example, a die-by-die method, and a detection pattern is also formed in a vacant region of one semiconductor device together with a circuit pattern of the semiconductor device. Is.

Next, (I) a detection pattern forming procedure and (II) a detection method using the detection pattern will be described. In the step (I) of forming the detection pattern, further in accordance with the manufacturing process of the semiconductor device, (A) lower layer pattern forming step, (B) interlayer insulating film and detection through hole forming step, and (C) upper layer pattern forming step. The process will be described separately.

(I) Detecting Pattern Forming Procedure (A) Lower Layer Pattern Forming Step After forming a conductor film on the upper surface of the semiconductor substrate 5 by the sputtering deposition technique, the lower layer pattern 10 is formed by the photolithography technique. To do. At this time, in the semiconductor device, a lower layer wiring having a predetermined pattern (not shown) is formed. As shown in FIG. 1, the lower layer pattern 10 has a predetermined wiring width L (for example, 100 μm) and is formed so as to extend in a misalignment direction corresponding to the arrow direction in FIG. Further, substantially square pad metal films 11 and 12 are formed on both ends thereof.

(B) Interlayer Insulating Film and Detection Through Hole Forming Step After the insulating film 25 is formed on the semiconductor substrate 5 which has completed the step (A) by the CVD technique, the photolithographic technique is used. For example, a rectangular through hole 20 for detection is formed in the insulating film 25 so as to straddle the lower layer pattern 10. Here, the size of the detection through-hole 20 is such that, for example, when each side is a, b, c, d, the two sides a and c in the direction x orthogonal to the lower layer pattern 10 surely straddle the lower layer pattern 10. In order to secure the opening, it is desirable that one side has a large margin of 1 μm or more, and it is desirable that the two sides b and d in the direction y parallel to the lower layer pattern 10 have a width of 2 μm or more for reliable opening of the detection through hole 20. This size does not have to be increased more than necessary in order to reduce the size of the entire detection pattern.

Also, through holes 21 and 22 are provided in the pad metal films 11 and 12 of the lower layer pattern 10. This is for measuring the electrical resistance of the lower layer pattern 10 performed after the process for detecting misalignment.

(C) Upper Layer Pattern Forming Step After forming a conductive film on the semiconductor substrate 5 which has completed the step (B) by using the sputtering deposition technique, the upper layer pattern 30 is formed by using the photolithography technique. To do.
The upper layer pattern 30 is formed, for example, in a rectangular shape so as to cover the detection through hole 20 in the direction x orthogonal to the lower layer pattern 10. At this time, when the upper layer pattern 30 is, for example, each side e, f, g, and h, relative to each side a, b, c, d of the detection through hole 20 as shown below. Form to have a relationship.

That is, of the two sides f and h having the direction y parallel to the lower layer pattern 10 and the two sides e and g of the direction x orthogonal to the lower layer pattern 20, they are displaced from the center of the through hole 20 for detection. The side g located on the y side in the same direction as the direction (arrow direction in the figure) in which the upper limit pattern 30 is to be detected has a margin of deviation D or more, for example, the upper layer pattern 30 has a margin of plus 1 μm with respect to the margin of deviation D for detection. The through hole 20 is covered. On the other hand, the piece e which is orthogonal to the lower layer pattern 10 and is located in the direction opposite to the direction in which the deviation should be detected when viewed from the center of the through hole 20 for detection has a margin of the deviation allowable value D or less and the upper layer pattern 30 has a margin. The detection through hole 20 is covered. The deviation allowable value D is an arbitrary value determined by how much deviation should be detected by a person who uses this detection pattern. In this embodiment, it is 0.3 μm.

In this step, the through hole 2 is further added.
Pads 31 and 32 are formed at the opening positions of 1 and 22, respectively.

(II) Detection Method Using Detection Pattern FIG. 4 is a partial plan view of the detection pattern of FIG. 1, and is a diagram showing an example in which misalignment occurs so that misalignment is detected. .. FIG. 5 is a cross-sectional view taken along the line AB of FIG.

During the manufacturing of the semiconductor device, in the photolithography process of the through hole and the upper layer wiring in the upper layer pattern forming step (C), there is a misalignment of the detection through hole 20 and the upper layer pattern 30 which is more than the allowable deviation value D. When it occurs, as shown in FIG. 4, the upper layer pattern 30 does not cover the detection through hole 20 at the side e where the detection through hole 20 and the upper layer pattern 30 have a small overlap margin.
In such a state, as shown in FIG. 5, due to over-etching at the time of etching for forming the upper layer pattern 30, even the lower layer pattern 10 exposed on the bottom surface of the detection through hole 20 not covered by the upper layer pattern 30. The peach will be etched. Further, since the detection through hole 20 crosses over the lower layer pattern 10, the etching of the lower layer pattern 10 is also performed so as to cross the lower layer pattern 10. As a result, the lower layer pattern 10 crosses the etching.

After the photolithography process is completed through the above process, the measuring probe of the resistance measuring device 40 is applied to the pads 31 and 32 to measure the electric resistance between the pad metal films 11 and 12 of the lower layer pattern 10. For example, if the lower layer pattern 10 is broken, the resistance value becomes infinite, so that it can be understood that the resistance measuring device 40 causes a misalignment regardless of visual observation with an optical microscope or the like.

Further, as shown in FIG. 5, conditions for etching the upper layer pattern 30 in the photolithography process,
For example, the lower layer pattern 10 may not be disconnected depending on conditions such as etching time. Even in this case, by increasing the wiring width of the lower layer pattern 10 to reduce the resistance and the like, and by repeatedly arranging a large number of detection patterns, for example, about 20 pieces, the resistance increment becomes clear and the resistance increment is determined. Can be detected by a resistance measuring device or the like.

On the other hand, if the misalignment amount is within the allowable range taken as the alignment margin D, the upper layer pattern 30 completely covers the through hole 20, the photolithography process is normally completed, and the lower layer pattern 10 is not etched. , No disconnection. In this way, the product inspection of the semiconductor device can be performed by measuring the resistance value.

The present embodiment has the following advantages.

(A) The misalignment between the through hole 20 and the upper layer pattern 30 is converted into a disconnection phenomenon of the lower layer pattern 10 caused by over-etching after the photolithography process, and both sides of the detection through hole in the lower layer pattern 10 are separated. The electrical resistance between the pad metal films 11 and 12 is measured. Therefore, it is possible to perform the measurement with the normal resistance measuring device 40, and it is possible to detect the misalignment between the through hole 20 and the upper layer pattern 30, that is, the misalignment between the through hole and the upper layer wiring in the semiconductor device.
This simplifies the inspection of misalignment and shortens the time required for the inspection. Particularly, by using a fully-automated measuring device, 100% inspection of semiconductor device products can be performed relatively easily. Further, the semiconductor devices are sorted by electrically measuring all of them after the process is completed, but according to this method, it is possible to perform the sorting at the same time as the sorting, and no special inspection is required.

(B) In the detection pattern of the present invention, as the detection means, a defect that occurs when misalignment occurs in an actual semiconductor device product, for example, overetching disconnection is emphasized. Therefore, by using this detection pattern, it can be determined whether or not the misalignment amount is an allowable amount. In this way, not only product inspection,
It can also be used to evaluate the alignment margin at the product development stage.

FIG. 6 is a plan view of another detection pattern used in the embodiment of the present invention.

This detection pattern is different from the detection pattern of the above-described embodiment in that the misalignment detection is performed in one direction in FIG. 1, but the misalignment detection is further performed in four directions.

In this detection pattern, the lower layer pattern 10
-1 is formed in a cross shape as shown in the drawing, and the same detection patterns as those in FIG. 1 are formed in four directions on the respective lower layer patterns 10-1a to 10-1d. Then, pads 13, 14, 15, and 16 are formed at the ends of the lower layer patterns 10-1a to 10-1d, respectively. In this detection pattern, during manufacturing of a semiconductor device, one of the lower layer patterns 10-1a to 10-1d due to overetching may be formed in a direction in which the upper layer pattern 30-1 does not cover the detection through hole 20-1 in the photolithography process. Since disconnection or erosion occurs, −, −,
By measuring the electrical resistance between − and −, it is possible to know the direction of misalignment from any of the lower layer patterns 10-1a to 10-1d having a high resistance value.

FIG. 7 is a plan view of another detection pattern used in the embodiment of the present invention.

In this detection pattern, as in FIG. 6, the lower layer pattern 10-2 is formed in a cross shape, and a substantially square detection through hole 20-2 is opened at the intersecting portion, and this through hole 20 is formed. -2, the upper layer pattern 30-2 is formed to be larger by the alignment margin D so as to cover -2. Even in this way,-,-in the figure
By measuring the electrical resistance between −, −, −, the direction in which the misalignment occurs can be known, and the advantages similar to those in the case of FIG. 6 can be obtained, and the formation of the detection pattern is simplified.

The embodiment of the present invention is not limited to the above embodiment, but various modifications can be made. Examples of such modifications include the following.

(I) In the above-described embodiment, the lower layer wiring of the semiconductor device, the interlayer insulating film in which the through hole is formed, the upper layer wiring, the lower layer pattern 10, the detection through hole 20,
Although the upper layer pattern 30 is formed of three layers, it can be applied to various semiconductor devices in which the number of layers is further increased.

(Ii) In FIG. 7, the detection through hole 20-2 and the upper layer pattern 30-2 are formed in a substantially square shape, but they may have other shapes such as a circle.

(Iii) Lower layer pattern 1 of FIGS. 1 and 6
A plurality of detection through holes 20 and 20-1 are arranged on the 0 and 10-1 along the misalignment detection direction at intervals, and the respective detection through holes 2 are arranged.
If the upper layer patterns 30 and 30-1 are formed on the layers 0 and 20-1, they function as vernier, and by measuring the resistance value thereof, the misalignment amount can be measured.

(Iv) The detection patterns shown in FIGS. 1, 6, and 7 may be formed in a circuit pattern that constitutes a semiconductor device. Even in this case, since the misalignment can be detected, the product inspection can be performed while also evaluating the misalignment at the product development stage.

[0048]

As described in detail above, according to the present invention, the measurement of the detection pattern is related to the etching state in the photolithography process, and the measurement is performed between predetermined positions on both sides of the detection through hole in the lower layer pattern. Since the resistance value is measured, a defect of the semiconductor device due to overetching can be indirectly detected after the photolithography process is completed. In this way, the misalignment between the through hole of the semiconductor device and the upper layer wiring is detected by electrical measurement, so that the inspection can be simplified and can be performed in a short time. Further, it can be used for evaluating the alignment margin in increasing the density of the multilayer wiring.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a detection pattern used in an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a conventional detection pattern.

FIG. 3 is a diagram showing two conventional wiring configuration examples with different alignment margins.

FIG. 4 is a partial plan view of the detection pattern of FIG.

5 is a cross-sectional view taken along the line AB of FIG.

FIG. 6 is a plan view of another detection pattern used in the embodiment of the present invention.

FIG. 7 is a plan view of another detection pattern used in the embodiment of the present invention.

[Explanation of symbols]

 5 semiconductor substrate 25 interlayer insulating film 10 lower layer pattern 20 through hole for detection 30 upper layer pattern

Claims (1)

Claim: What is claimed is: 1. On a semiconductor substrate, a lower layer wiring, an interlayer insulating film having a through hole formed therein, and an upper layer wiring connected to the lower layer wiring through the through hole are sequentially laminated. In a method of detecting a misalignment between a through hole and an upper layer wiring, which detects misalignment between the through hole and the upper layer wiring by using a detection pattern provided in an empty region of the semiconductor device during manufacturing of the semiconductor device, The detection pattern includes a lower layer pattern that is disposed between the semiconductor substrate and the interlayer insulating film when the lower layer wiring is formed, and extends in the misalignment detection direction with a predetermined wiring width, and the wiring width that straddles the lower layer pattern. A detection through hole that is made larger in the interlayer insulating film, and an alignment margin equal to the detection displacement amount to be detected at a position corresponding to the alignment displacement detection direction. And an upper layer pattern that intersects the lower layer pattern so as to cover the detection through hole, and the resistance value between predetermined positions on both sides of the detection through hole in the lower layer pattern is configured by using this detection pattern. Is measured and the misalignment between the through hole and the upper layer wiring is detected based on the resistance value.
Method for detecting misalignment of upper layer wiring.