KR20000045238A - Apparatus and method for measuring overlay used in semiconductor manufacturing process - Google Patents

Abstract

PURPOSE: Apparatus and method for measuring an overlay between layers of a semiconductor element are provided to improve the semiconductor manufacturing process and to make it possible to analyze the fault of the semiconductor element by measuring an electric resistance value between layers of the semiconductor element. CONSTITUTION: A first measuring pattern(21) having a plurality of sub-pattern layers is provided in a form of a finger. A second measuring pattern(22) having an identical structure to the first measuring pattern(21) is provided with plural sub-pattern layers which are inserted between the sub-pattern layers of the first measuring pattern(21). A first wire(26a) connects resistance layers to each other and a first pad layer(25a) is connected to the first wire(26a). A second wire(26b) connects a main pattern layer of the first measuring pattern(21) and a main pattern layer of the second measuring pattern(22). A second pad layer(25b) is connected to a third wire(26c), which is connected to a main pattern layer of a fourth pattern.

Description

Overlay measuring device and method in semiconductor device manufacturing process

The present invention relates to the measurement of the degree of alignment of semiconductor devices. In particular, the degree of misalignment-alignment between layers in a device manufacturing process can be known by measuring the electrical resistance value after Fab-out. The present invention relates to an overlay measuring apparatus and method in a semiconductor device manufacturing process enabling defect analysis.

In general, when one pattern is formed in a semiconductor device manufacturing process, it is determined whether the alignment of the pattern is accurate or within an error range.

In the pattern measurement, a target area as a measurement target and an alignment layer as a reference for measurement are used.

Two measurement patterns are formed independently in the X direction and the Y direction, and the alignment or misalignment is determined by observing whether the alignment area and the target area coincide.

Typically, the measurement pattern is formed in a direction parallel to the flat zone direction to determine the alignment state in the X direction based on whether the target area and the alignment area correspond to the left and right or up and down.

Then, the alignment state in the Y direction is determined based on the alignment state in the 90 ° rotated direction in the flat zone.

Hereinafter, the overlay measurement of the prior art will be described with reference to the accompanying drawings.

1A and 1B are schematic diagrams of test patterns during overlay measurement in the prior art.

In the prior art overlay measurement pattern formation, first, as shown in Figure 1a, the first measurement pattern (1) in the form of a square photo / etched, the second measurement pattern (2) to the center of the first measurement pattern (1) Place the photo on and pattern the photo by etching.

After patterning the first and second measurement patterns (1) and (2) as described above, the distance between the first measurement pattern 1 and the second measurement pattern 2 in the AA and BB directions is measured using a dedicated overlay measurement device or SEM. Measure the size to measure the degree of overlay.

In another overlay measurement method of the related art, a method of measuring an overlay degree by measuring a separation distance between a first measurement pattern 3 and a second measurement pattern 4 having a finger shape as shown in FIG. 1B. There is this.

That is, after determining the separation distance between the first and second measurement patterns (3) and (4) in consideration of the misalignment degree (sizing), and checking the distance between the first and second measurement patterns with an optical microscope to determine the overlay degree To decide.

Such overlay measurement in the prior art has the following problems.

In the first measurement method of the related art, in which the measurement pattern has a rectangular shape, accuracy can be guaranteed when using dedicated measurement equipment, but the number of measurement samples is limited to through-put, so that the measured or Even with other chips, there is a problem in that the degree of overlay cannot be measured after the Fab-out.

In the second conventional measuring method, the overlay can be measured after fab-out, but the accuracy of the overlay is very low by measuring the degree of overlay with an optical microscope.

The present invention has been made to solve such a problem of the overlay measurement of the prior art, the process of making the misalignment-alignment between the layers in the device manufacturing process can be known by measuring the electrical resistance value after the Fab-out An object of the present invention is to provide an overlay measuring apparatus and method in a semiconductor device manufacturing process that enables process improvement and failure analysis in progress.

1A and 1B are schematic diagrams of test patterns in overlay measurement in the prior art.

2a and 2b is a test pattern configuration when overlay measurement according to the present invention

3A to 3D are layout diagrams showing a procedure of forming test patterns in overlay measurement according to the present invention.

4A and 4B are circuit configuration diagrams according to test pattern alignment.

5 is a graph illustrating a misalignment-alignment relationship between the measured resistance value and the resistance of the test pattern

Explanation of symbols for main parts of the drawings

21. First Measurement Pattern 22. Second Measurement Pattern

23. Space size between first and second measurement patterns 24. Resistance R

25. Pad 26. Wiring

Overlay measurement in the semiconductor device manufacturing process according to the present invention enables the improvement of the process and the failure analysis in the process by making the degree of misalignment-alignment between the layers can be known by measuring the electrical resistance value after the Fab-out. The device comprises a plurality of sub-pattern layers connected to one main pattern layer, and repetitively configured in a rectangular shape, and configured in the same form as the first measurement pattern and the first measurement pattern, which are configured in the form of a finger, for the first measurement. A measurement 1,2,3,4 pattern composed of a second measurement pattern composed of sub-pattern layers sandwiched between the sub-pattern layers of the pattern so as to correspond to each other; A first wiring layer connecting the resistor R layer configured to the main pattern layer of the second measurement pattern and the resistance R layers configured to the respective measurement patterns, and a first pad layer connected to the first wiring; A second wiring connecting the main pattern layer of the first measurement pattern and the main pattern layer of the second measurement pattern to each other; And a second pad layer connected to a third wiring connected to the main pattern layer of the measurement 4 pattern, wherein the overlay measurement method in the semiconductor device manufacturing process according to the present invention is performed during the manufacturing process of the semiconductor device. In the operation of measuring the overlay, it is characterized in that for measuring the overlay misalignment-alignment according to the resistance value measurement result of the contact area is changed according to the degree of alignment between the first measurement pattern and the second measurement pattern.

Hereinafter, an overlay measuring apparatus and method in a manufacturing process of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are schematic diagrams of test patterns during overlay measurement according to the present invention.

2A is for measuring the degree of overlay in the Y direction, Figure 2B is for measuring the degree of overlay in the X direction.

According to the present invention, four test patterns for each direction are configured by dividing the layers into ± X and ± Y directions in consideration of overlay between layers.

The configuration includes a first measurement pattern 21 and a first measurement pattern 21, each of which includes a plurality of sub-pattern layers that are connected to the main pattern layer with a plurality of sub-pattern layers repeatedly formed in a rectangular shape and configured in the form of a finger. Repeated measurements 1, 2, 3, consisting of a second measurement pattern 22 which is configured in the same form and is configured to sandwich the sub pattern layers between the sub pattern layers of the first measurement pattern 21 so as to correspond to each other. A first wiring 26a and a first wiring 26 connecting the 4 patterns, the resistance R layer 24 configured to be connected to the main pattern layer of the second measurement pattern 22, and the resistance R layer 24 configured to each measurement pattern; The first pad layer 25a connected to the first wiring 26a and the second wiring 26b connecting the main pattern layer of the first measurement pattern 21 and the main pattern layer of the second measurement pattern 21 to each other. And a second pad layer 25b connected to the third wiring 26c connected to the main pattern layer of the measurement 4 pattern. It is configured to include).

Here, the second wiring 26b connects the main pattern layer of the first measurement pattern 21 of the measurement 1 pattern and the main pattern layer of the second measurement pattern 22 of the measurement 2 pattern, and the first of the measurement 2 pattern. The main pattern layer of the measurement pattern 21 and the main pattern layer of the second measurement pattern 22 of the measurement 3 pattern are connected, and the main pattern layer of the first measurement pattern 21 and the measurement 2 pattern of the measurement 1 pattern 2 Connect the main pattern layer of the measurement pattern 22.

In the measurement 1 pattern, the separation distance between the first and second measurement patterns 21 and 22 is 0,09 µm, and the separation distance between the first and second measurement patterns 21 and 22 of the measurement 2 pattern is 0.06 µm.

The separation distance between the first and second measurement patterns 21 and 22 of the measurement 3 pattern is 0.03 μm, and the separation distance between the first and second measurement patterns 21 and 22 of the measurement 4 pattern is 0.00 μm.

In the overlay measuring apparatus according to the present invention configured as described above, two measuring patterns are configured on the wafer to measure the X and Y directions.

The formation order of the overlay measurement pattern according to the present invention is as follows.

3A to 3D are layout diagrams illustrating a procedure of forming a test pattern during overlay measurement according to the present invention.

The test pattern at the time of overlay measurement is formed as follows as the actual device process progresses.

First, as shown in FIG. 3A, the resistance R layer 24 is formed using a well or an active resistor by adjusting length or width.

As shown in FIG. 3B, a first measurement pattern 21 including a plurality of sub-pattern layers repeatedly formed in a rectangular shape and connected to one main pattern layer as a center is formed.

Subsequently, as shown in FIG. 3C, the second measurement is configured in the same form as the first measurement pattern 21 and is formed in such a manner that the sub pattern layers are inserted to correspond to each other between the sub pattern layers of the first measurement pattern 21. The pattern 22 is formed.

At this time, the measurement 1, 2, 3, 4 pattern is formed at the same time, the measurement 1 pattern, the separation distance between the first and second measurement patterns 21, 22 is 0,09㎛, the first and second measurement of the measurement 2 pattern The separation distance between the patterns 21 and 22 is 0.06 μm, and the separation distance between the first and second measurement patterns 21 and 22 of the measurement 3 pattern is 0.03 μm and the first and second measurement patterns 21 and 22 of the measurement 4 pattern. The distance between the gaps is formed to be 0.00㎛.

As shown in FIG. 3D, the first pad layer 25a connected to the first wiring 26a and the first pad layer 25a and the first measurement connected to the resistor R layers 24 included in each measurement pattern. The second wiring 26b connecting the main pattern layer of the pattern 21 and the main pattern layer of the second measurement pattern 21 to each other, and the third wiring 26c connected to the main pattern layer of the measurement 4 pattern. The second pad layer 25b is formed.

The overlay measurement method using the overlay measurement apparatus according to the present invention configured as described above proceeds as follows.

4A and 4B are circuit diagrams according to test pattern alignment, and FIG. 5 is a graph showing a misalignment-alignment relationship between the measured resistance value and the resistance of the test pattern.

The overlay measurement method of the present invention has a circuit configuration as shown in FIG. 4B by using a contact area that varies according to the degree of alignment between the first measurement pattern 21 and the second measurement pattern 22 as in FIG. 4A. The overlay misalignment-alignment is determined according to the resistance measurement result of the overlay measurement apparatus of the present invention.

If χ ⁰ , χ ¹ , χ ² , χ ³ ≪ R in FIG. 4B,

If the measurement is shorted to χ ⁰ , the R measurement is 1R. If the measurement is shorted to χ ¹ , the R measurement is shortened to R / 2, χ ^2. If the R measurement is shorted to R / 3, χ ³ , the R measurement is R / 4. .

The overlay measurement apparatus according to the present invention creates a test pattern in consideration of the overlay for each direction. When the misalignment occurs in each specialized direction, the first and the second measurement pattern 21 (the first and the second test patterns 21) The contact area between the electrodes 22 is increased so that the resistance value decreases as the test pattern is smaller.

The misalignment is generated between the first and second measurement patterns 21 and 22 in the ± X and ± Y directions in accordance with the alignment change occurring in the photo process.

That is, in the test patterns separated in four directions of ± X and ± Y, the contact resistance is formed as shown in FIG. 4A according to the separation distance, and in the test pattern having a small separation distance, the resistance value is increased as the contact area increases. Becomes smaller than the wide part.

If the test pattern has a larger separation distance than the misalignment magnitude generated between the first and second measurement patterns 21 and 22, it is represented as an open resistance value that is not electrically connected.

This means that the magnitude of misalignment generated is within the separation distance of the electrically open test pattern and one step lower.

In view of the above, it can be seen that the resistance value increases in the direction in which misalignment occurs as the separation distance between the first and second measurement patterns 21 and 22 increases.

Such electrical characteristics appear because the circuit configuration of the overlay test pattern according to the present invention has a resistance value of parallel connection as shown in FIG. 4B.

If the contact resistance between the first and second measurement patterns 21 and 22 is much smaller than the resistance R layer 24 for improving the discriminating power of the data, the misalignment range can be identified by the resistance measurement value of the entire test pattern. The relation is as described above.

The overlay measurement value in the process according to the ratio of the resistance measured between the first and second pads 25a and 25b and the resistance R layer 24 is within the separation distance between the first and second measurement patterns 21 and 22. It can be seen that.

The misalignment relationship according to the ratio of the measured resistance value and the resistance R layer 24 is as shown in FIG. 5.

Such an overlay measuring apparatus and method in a semiconductor device manufacturing process according to the present invention has the following effects.

The degree of overlay between the layers can be measured electrically from the wafer, making measurement easier and increasing accuracy.

This has the effect of defect analysis and process improvement according to the process.

Claims (8)

A first measurement pattern comprising a plurality of sub-pattern layers connected to one main pattern layer in a rectangular shape and repeatedly configured in a rectangular shape, the first measurement pattern having a finger shape, and the same shape as the first measurement pattern, Repeated measurement 1,2,3,4 patterns consisting of a second measurement pattern composed of sub pattern layers sandwiched between the sub pattern layers so as to correspond to each other; A first wiring layer connecting the resistor R layer configured to the main pattern layer of the second measurement pattern and the resistance R layers configured to the respective measurement patterns, and a first pad layer connected to the first wiring; A second wiring connecting the main pattern layer of the first measurement pattern and the main pattern layer of the second measurement pattern to each other; And a second pad layer connected to a third wiring connected to the main pattern layer of the measurement 4 pattern. The main wiring of claim 1, wherein the second wiring connects the main pattern layer of the first measurement pattern of the measurement 1 pattern and the main pattern layer of the second measurement pattern of the measurement 2 pattern, and the main pattern of the first measurement pattern of the measurement 2 pattern. Connecting the layer and the main pattern layer of the second measurement pattern of the measurement 3 pattern, and connecting the main pattern layer of the first measurement pattern of the measurement 1 pattern and the main pattern layer of the second measurement pattern of the measurement 2 pattern. Overlay measuring device in semiconductor device manufacturing process. The method of claim 1, wherein the measurement 1 pattern has a separation distance of 0,09 mu m between the first and second measurement patterns, the separation distance of the first and second measurement patterns of the measurement 2 pattern is 0.06 mu m, and the first, 2. The separation distance between the measurement patterns is 0.03 μm, and the separation distance between the first and second measurement patterns of the measurement 4 pattern is 0.00 μm. The semiconductor device according to claim 1, wherein the test pattern consisting of the measurement 1,2,3,4 patterns is configured to correspond to the X direction and the other is configured to correspond to the Y direction to measure the X and Y directions. Overlay measuring device in device manufacturing process. The first and second measurement patterns of claim 1, wherein when a misalignment occurs between the first and second measurement patterns in the ± X and ± Y directions according to an alignment change occurring in the photo process, the test pattern having a smaller separation distance is used. An overlay measurement apparatus in a semiconductor device manufacturing process, characterized in that the contact area between the pores increases and the resistance value decreases. The resistance value according to the contact area between the first and second measurement patterns in the test pattern consisting of the measurement 1,2,3,4 patterns is respectively χ ⁰ , χ ¹ , χ ² , χ ^3. ≪ If R is shorted to χ ⁰ , R measured value is 1R, if χ ^{1 is} shorted, if R measured value is shorted to R / 2, χ ² , R is measured to R / 3, χ ³ , R is measured Is R / 4, the overlay measuring apparatus in the semiconductor device manufacturing process characterized by the above-mentioned. The overlay measuring apparatus of claim 6, wherein the test pattern having a separation distance wider than the misalignment magnitude generated between the first and second measurement patterns is represented as an open resistance value which is not electrically connected. . In the operation of measuring the overlay during the manufacturing process of the semiconductor device, It comprises a plurality of sub-pattern layer which is connected to the main pattern layer in the center and is repeatedly configured in a rectangular shape and is configured in the same form as the first measurement pattern and the first measurement pattern configured in the form of a finger By using a repeating test pattern consisting of a second measurement pattern consisting of a shape sandwiched between the sub pattern layers to correspond to each other; The overlay misalignment-alignment method of the semiconductor device manufacturing process, characterized in that for measuring the overlay misalignment degree according to the resistance measurement results of the contact area is changed according to the degree of alignment between the first measurement pattern and the second measurement pattern.