JPH0230173B2 - - Google Patents

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a mask formed on a semiconductor wafer in order to evaluate the precision of mask alignment for photolithography during the manufacture of semiconductor devices. Concerning vernier patterns for evaluating alignment accuracy.

(Prior Art) A vernier for evaluating mask alignment accuracy is used in conventional semiconductor wafers to evaluate the accuracy of mask alignment for photolithography during the manufacturing process, separately from the circuit pattern of the element to be formed. A pattern is formed. Various types of vernier patterns are known, but
One of them is a two-layer Vernier pattern that is formed simultaneously with a conductive film for a circuit pattern formed by two photolithography processes (Digest of Technical Papers. 1984).
Symposium on VLSI Technology, P.62-63,
This is especially shown in Figure 1) on page 63. The plan view of this vernier pattern is shown in Fig. 5a, and its B-
A sectional view taken along line B' is shown in FIG. 5b. That is, 5
1 is a semiconductor substrate, 52 is an insulating film on the substrate 51, and L1 and L2 are a first layer conductive film and a second layer conductive film formed in the insulating film 52 as a vernier pattern. In this case, the first layer conductive film L
1 is a plurality of rectangular conductive film patterns 53;
... are arranged in the lateral direction at a constant pitch _P1 , and the second layer conductive film L2 has a plurality of rectangular conductive film patterns 54 arranged at a constant pitch _P different from the above-mentioned constant pitch P1. ₂ arranged horizontally. Therefore, the results of conducting a continuity test to determine the presence or absence of electrical contact between the corresponding patterns of the first-layer conductive film pattern 53 and the second-layer conductive film pattern 54 are used for mask alignment. By comparing this with the conduction state that should be obtained in a state where no misalignment occurs, it becomes possible to detect the presence or absence of mask alignment misalignment and the extent of the misalignment. In this case, by providing vernier patterns such as those described above in the X and Y directions on the semiconductor wafer, it becomes possible to detect mask misalignment in the X and Y directions.

However, in the case of the vernier pattern described above, the detection accuracy of misalignment is limited to the conductive film pattern 5 of the first layer.
3 Pitch P ₁ and second layer conductive film pattern 5
Since it is determined by the difference (for example, 0.1 μm) from the pitch P ₂ of 4..., it cannot meet the recent strict demands for alignment accuracy. Therefore, in order to meet this requirement, it is possible to reduce the above pitch difference, but it is necessary to increase the number of conductive film patterns in each layer in order to make it possible to detect misalignment. As a result, the area occupied by the vernier pattern on the semiconductor wafer becomes large, and the wafer utilization efficiency decreases.

Note that the vernier pattern is formed such that the direction of displacement of the second layer conductive film with respect to the first layer conductive film is different on both sides of the array center portion. This is due to variations in the contact state between the two-layer conductive films caused by variations in the rectangular pattern width when forming the first-layer conductive film or variations in the rectangular pattern width when forming the second-layer conductive film, and the mask alignment deviation. This is done in order to cause a difference in the detection results due to the variation in the contact state between the two-layer conductive films caused by this, thereby making it possible to accurately detect mask misalignment.

(Problems to be Solved by the Invention) The present invention has been made to solve the problem that the detection accuracy of mask misalignment is low as described above. It is an object of the present invention to provide a vernier pattern for evaluating mask alignment accuracy that does not require an increase in the number of conductive film patterns and occupies a small area on a semiconductor wafer.

[Structure of the invention]

(Means for Solving the Problems) The vernier pattern for evaluating mask alignment accuracy of the present invention is a method in which a plurality of conductive film patterns having a constant shape are arranged horizontally at a constant pitch as a first layer conductive film in an insulating film on a semiconductor substrate. A plurality of conductive film patterns having a fixed shape are arranged in the horizontal direction at a fixed pitch different from the pitch as the second layer conductive film, and are formed to face the first layer conductive film. It is characterized by being

(Function) The capacitance between each set of conductive film patterns facing each other above and below the two-layer conductive film formed as described above is proportional to the opposing area of each set of conductive film patterns, and this opposing area is Since it changes in an analog manner according to mask misalignment in the pattern arrangement direction, by measuring the capacitance, it is possible to detect the degree of mask misalignment as an analog quantity with high precision.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a cross-sectional structure of a vernier pattern forming section for evaluating mask alignment accuracy provided in each of the X direction and Y direction on a semiconductor wafer. That is, 1 is a semiconductor substrate, 2 is an insulating film on the substrate 1, and L1 and L2 are first insulating films formed as vernier patterns in the insulating film 2.
The layer conductive film and the second layer conductive film are opposed to each other with an interlayer insulating film 2' interposed therebetween. The first layer conductive film L1 has a plurality of (5 in this example) conductive film patterns 3 having a constant width W (for example, 1.0 μm) arranged in the horizontal direction at a constant pitch _P1 . It is formed. In addition, the second layer conductive film L
2, a plurality of (5 in this example) conductive film patterns 4 having a pattern of a constant width W are arranged at the above pitch.
They are formed so as to be arranged in the horizontal direction at a constant pitch _P2 different from _P1 . In this case, in this example, the pitch P 2 of the conductive film pattern _{4 of the second layer is larger than the pitch P 1} of the conductive film pattern 3 of the first layer, and the mask used when forming the conductive film pattern of each of these layers is larger than the pitch P ₁ of the conductive film pattern 3 of the first layer. 1 at the center position in each arrangement direction when there is no misalignment.
A pair (upper and lower) of conductive film patterns 3 and 4 (hereinafter referred to as 3 ₀ ,
4 ₀ ) are formed so that they completely face each other. In this state, as the distance from the center position increases, the opposing positions of the sets of conductive film patterns that face each other in the upper and lower directions shift sequentially, and the amount of shift d gradually increases. Then, the amount of positional deviation d in this state
, one set of conductive film patterns 3 ₀ and 4 ₀ at the center position is zero, and each of the other sets changes in units of the difference (for example, 0.1 μm) between the pitches P ₁ and P ₂ . + for each group on the right side of the position
0.1 μm, +0.2 μm, −0.1 μm, −0.2 μm for each set on the left side of the center position. In other words,
The facing area of one set of conductive film patterns 3 ₀ and 4 ₀ at the central position is the largest, and the facing area of each set of conductive film patterns becomes smaller as the distance from this central position increases.

Therefore, in the case of the above-mentioned evaluation vernier pattern, when the capacitance is measured for each set that faces each other at the top and bottom, the capacitance value for each set when no mask misalignment occurs is as shown in Fig. 2. The capacitance value of one set at the center position is the largest, and the capacitance value of each set becomes smaller as you move away from it. On the other hand, the second layer conductive film L2 is moved toward the right in FIG. 1 with respect to the first layer conductive film L1, for example.
The capacitance value of each set with a deviation of 0.05 μm is the second
As shown by the circle in the figure, compared to the state where there is no mask misalignment, the capacitance values of the center position and each set to the right of it decrease by an analog amount corresponding to the amount of mask misalignment, and are lower than the center position. The capacitance value of each set on the left increases by an analog amount corresponding to the amount of mask misalignment. In this case, the intersection point X of the straight line U connecting the increased capacitance values of each group and the straight line D connecting the decreased capacitance values of each group is to the left of the center position.
Since there will be a deviation of 0.05 μm, the above-mentioned intersection point X is determined based on the measurement results of each capacitance value, and by further determining the amount of deviation Δ between it and the center position, the amount of mask alignment deviation can be determined in units of the pitch difference of 0.1 μm. It becomes possible to detect a smaller analog quantity with high precision, making it possible to increase the precision by about 10 times.

As an example of the planar pattern of each set of conductive film patterns, a case where the amount of positional deviation d is not zero is shown in FIG. It is a pattern, and each electrode (pad 3', 4') with a wide area is formed in a row at the end to contact the probe needle of a wafer prober for capacitance measurement and apply a potential. Each pad 3', 4' is exposed on the wafer so that it can be contacted by a probe needle.

In addition, if the probe needle can be brought into direct contact with the conductive film pattern by using a high-precision wafer prober, the formation of the pad can be omitted and the area occupied by the vernier pattern forming section can be reduced accordingly. It becomes possible to do so.

Further, by forming a large capacitance value between each set of conductive film patterns, the change in the capacitance value due to mask misalignment becomes large, so that detection accuracy can be improved. for that purpose,
In order to increase the area of each set of conductive film patterns, two conductive film patterns 3 ₁ and 3 ₂ are formed in parallel in the first layer and commonly connected for each set, as shown in FIG. 4, for example. Also in the second layer, two conductive film patterns 4 ₁ and 4 ₂ may be formed in parallel to make a common connection.

〔Effect of the invention〕

As described above, according to the vernier pattern for mask alignment accuracy evaluation of the present invention, by forming the two-layer conductive film so that the opposing areas are sequentially shifted without increasing the number of patterns of the two-layer conductive film, Since the degree of mask misalignment can be detected with high accuracy without increasing the area occupied by the semiconductor wafer, it is extremely effective when applied to the manufacture of semiconductor devices that require highly accurate mask alignment.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a vernier pattern forming part for evaluating mask alignment accuracy in a semiconductor wafer according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of each set of conductive film patterns facing each other vertically in the vernier pattern of FIG. 3 is a characteristic diagram showing the relationship between the capacitance measurement value and the amount of mask misalignment; FIG. 3 is a planar pattern diagram showing an example of one set of conductive film patterns taken out of the vernier pattern in FIG. 1; FIG. Planar pattern diagram showing a modification of the pattern in Figure 3, Figure 5.
FIG. 5a is a plan pattern diagram showing an example of a conventional vernier pattern, and FIG. 5b is a sectional view taken along line BB' in FIG. 5a. 1... Semiconductor substrate, 2, 2'... Insulating film, 3,
3 ₀ ... Conductive film pattern (first layer), 4,4 ₀ ...
Conductive film pattern (second layer), 3', 4'...pad.

Claims (1)

[Claims] 1 Two layers of conductive films vertically facing each other with an interlayer insulating film interposed in an insulating film on a semiconductor substrate are formed separately from the circuit pattern of the element, and the conductive films of each layer are A plurality of conductive film patterns each having a certain shape are arranged in the horizontal direction, and the arrangement pitch of the first layer conductive film pattern and the arrangement pitch of the second layer conductive film pattern are different, and each conductive film pattern has a different arrangement pitch. A vernier pattern for evaluating mask alignment accuracy, characterized in that a pad formed for each part or each conductive film pattern is exposed on the wafer. 2. The conductive film patterns of each layer are formed such that a pair of conductive film patterns above and below the center position in the arrangement direction is formed so that there is no deviation in opposing positions with no mask misalignment, and the center position in the arrangement direction is 2. The vernier pattern for evaluating mask alignment accuracy according to claim 1, wherein the directions of the opposing positions of the conductive film patterns of each set are opposite to each other on both sides of the pattern.