JPH0432216A - Evaluation of overlay accuracy and dimension accuracy - Google Patents

Abstract

PURPOSE:To evaluate an overlay accuracy and a dimension accuracy in a short time by locating a first verification pattern on each side of both arms of a second verification pattern for checking the state between the first and second verification patterns, conducting or nonconducting, and for measuring a resistance value of the second verification pattern. CONSTITUTION:In the case that an overlay error between an actual basic pattern and a desired mask pattern is within the tolerance, the space between an arm 9a of a second verification pattern 9 and each of first verification patterns 8a and 8b is in the nonconducting state since one arm 9a of the second verification pattern 9 is located between the first verification patterns 8a and 8b. It is checked if the state of the spaces between the arm 9a of the second verification pattern 9 and each of the first verification patterns 8a and 8b and between the other arm 9b of the second verification pattern 9 and each of the other first verification patterns 8c and 8d are conducting or nonconducting. In the case that every space proves to be in the nonconducting state after the check, it is estimated that the overlay error between the actual basic pattern and the desired mask pattern is within the tolerance. In the case that any one space proves to be in the conducting state, it is estimated that the overlay error exceeds the tolerance. In this case, the direction of the overlay deviation can be specified by knowing which verification pattern is in the conducting state.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention improves the overlay accuracy and dimensional accuracy when forming fine patterns using photolithography and etching techniques in the manufacturing process of semiconductor integrated circuit devices. The present invention relates to a method for evaluating overlay accuracy and dimensional accuracy to be inspected and evaluated.

[Conventional technology]

Conventionally, as a method for evaluating the overlay accuracy between a conductive base pattern on a substrate and a desired mask pattern formed on a photosensitive resin film (hereinafter referred to as resist) thereon, the method shown in Fig. 7 has been used. A method called the Vernier method was used to read overlay errors through visual inspection by transferring evaluation patterns with different pitches.

On the other hand, as a method for evaluating the dimensional accuracy of a desired mask pattern formed in a resist on a base pattern, the dimensional accuracy is evaluated by measuring the dimensions of a monitor pattern formed in the same process as the actual desired mask pattern. was.

By the way, to explain in detail the Vanier method, which is a method for evaluating overlay accuracy, as shown in FIG.
Five first patterns 2a, 2b, 2C, 2 with a constant width
d, 2e, and each of these first patterns 2a to 2
e, second patterns 3a, 3b, 3. c.
, 3d.

Form 3e.

At this time, each of the first patterns 2 of the second patterns 3a to 3e
The positional deviation amount d for a to 2e is (Lfl) 15, which is set to a value that corresponds to the accuracy actually required.

Then, it is visually determined whether the positional relationship between the underlying pattern and the desired mask pattern in the actual device matches any of the patterns on the substrate 1 shown in FIG. 7, and one of the patterns shown in FIG. With reference to the positional relationship of pattern 2C93C, which is the most even left and right at one place, for example, pattern 2b whose positional relationship is slightly shifted from this,
3b or patterns 2d and 3d, it is determined that the overlay error is d (-(L-1)15),
If it matches pattern 2a, 3a or pattern 2e, 3e, it is determined that the overlay error is 2·d, and the actual device pattern corresponds to which of the positional relationships of each pattern in FIG. 7. Determine the overlay error by
It is evaluated whether the overlay error between the actual base slam and the mask pattern is within an allowable range.

Next, to explain in detail the method for evaluating dimensional accuracy, a mask pattern to be transferred to the resist on the base pattern of the actual device and a monitor pattern with the same dimensions are simultaneously transferred to the resist, and the transferred monitor pattern is As shown in FIG. 8, the dimensions of the monitor pattern itself patterned on the monitor substrate 4 and transferred to the resist;
Or pattern 5 obtained by patterning on substrate 4
The dimensions of the mask pattern are measured by a well-known method such as an optical measurement method or a measurement method using an electron beam, etc., and the error from the design value is determined to evaluate the dimensional error of the mask pattern.

[Problem to be solved by the invention]

In the past, overlay accuracy evaluation and dimensional accuracy evaluation were performed in separate processes, but due to the design, these accuracy evaluations may be dependent on each other, so it is necessary to perform both accuracy evaluations in one process. However, since both evaluation steps are performed separately, there is a problem in that it takes a long time to comprehensively evaluate the accuracy.

Here, the evaluation of overlay accuracy and dimensional accuracy are dependent, which means that overlay accuracy is determined by the relative positional relationship between the underlying pattern and the mask pattern, and is influenced by the dimensions of the mask pattern and the accuracy of the dimensions of the underlying pattern. For example, if a mask pattern with a line width smaller than the standard size is formed on a base pattern with a line width larger than the standard size, the overlay error will eventually fall within the allowable range.

This invention was made to solve the above-mentioned problems, and makes it possible to evaluate overlay accuracy and dimensional accuracy in a short time based on the results of continuity and resistance measurement of conductive patterns. The purpose is to

[Means to solve the problem]

A method for evaluating overlay accuracy and dimensional accuracy according to the present invention includes a method for evaluating overlay accuracy and dimensional accuracy by combining a desired mask pattern transferred using photolithography onto a photosensitive resin film formed on a conductive base pattern on a substrate, and Overlay accuracy with patterns,
In the overlay accuracy and dimensional accuracy evaluation method for evaluating the dimensional accuracy of the mask pattern, a conductive first verification pattern is formed in the verification pattern formation area on the substrate by the same process as the base pattern, and ,
A conductive second verification pattern consisting of two orthogonal sides is formed in the verification pattern formation area on the substrate using a monitoring mask pattern formed in the same process as the mask pattern, and the second verification pattern is formed in the verification pattern formation area on the substrate. The first verification pattern is positioned on both sides of the pattern, and conduction/non-conduction between the first and second verification patterns, and the second
The method is characterized in that the overlay accuracy of the base pattern and the mask pattern and the dimensional accuracy of the mask pattern are evaluated by measuring the resistance value of the verification pattern.

[Effect]

In this invention, 1. Measure the conduction/non-continuity between the second verification patterns and the resistance value of the second verification pattern, and if both verification patterns are conductive or non-conductive, the overlay error between the actual underlying pattern and the mask pattern is determined respectively. It is evaluated as within or outside the acceptable range, and the second
The dimensional accuracy of the actual mask pattern is evaluated based on the error between the measured resistance value of the verification pattern and the design value.

In this way, the conduction/nonconduction of both verification patterns and the resistance value of the second verification pattern can be measured in a series of steps.
It is not necessary to evaluate overlay accuracy and evaluate dimensional accuracy in separate processes as in the past, and the evaluation process can be performed in a shorter time than in the past.

〔Example〕

FIG. 1 is a plan view schematically showing an embodiment of the overlay accuracy and dimensional accuracy evaluation method of the present invention, and FIG. 2 is a sectional view taken along the line AA' in FIG. 1.

As shown in FIGS. 1 and 2, a thin insulating film 7 is formed in the verification pattern formation area on the same substrate 6 by the same process as that for the conductive base pattern formed on the substrate 2 in the actual device pattern. First verification patterns 8a, 8b, 8c conductive through.

At the same time, a desired mask pattern is formed in the same process as the desired mask pattern transferred to one resist on the conductive base pattern.Also, using a monitoring mask pattern, two patterns perpendicular to the verification pattern formation area on the substrate 6 are formed. Sides 9a, 9b
A cross-shaped conductive second verification pattern 9 is formed.

At this time, the first verification patterns 8a and 8b are located at positions j~ on both sides of one side 9a of the second verification pattern 9, and the first verification patterns 8c are located on both sides of the other side b of the second verification pattern 9. , 8d are located in each verification pattern 8a to 8d.
Form 8d and 9.

(7) After completing a series of device forming processes, the verification pattern forming area is cut and separated and subjected to accuracy evaluation.

In addition, in FIG. 1, 10 is the verification pattern 8 of each node 1.
It is a measurement pad provided at one end of 8-8d, and 1-
Reference numeral 1 denotes measurement pads provided at both ends of both sides 9a and 9b of the second verification pattern 9.

Incidentally, the interval between the first verification patterns 8a and 8b is set to a value that takes into account an overlapping margin, for example, and the distance between the first verification patterns 8a and 8b is set to a value that takes into account an overlapping margin.

8d is the same, and on the other hand, both sides 9a and 9b of the second verification pattern 9 are, for example, the first verification pattern 8a to 8d.
In a series of forming steps 8d, alignment is performed with reference to alignment marks provided in advance.

Next, such verification patterns 88 to 8d.

A method for evaluating overlay accuracy and dimensional accuracy using 9 will be explained by taking various cases as shown in FIGS. 3 to 6 as examples. Here, in Figures 3 to 6 (
Figure a) is a partial plan view, and figure (1) is a sectional view taken along the dashed line in figure (a).

First, if the overlay error between the actual base pattern and the desired mask button is within the allowable range, as shown in FIG. Since side 9a is located, side 9a and the first
There is no conduction between each of the verification patterns 8a and 8b, and the resistance value between both ends of the side 9a becomes a predetermined value.

On the other hand, if the overlay error is within the allowable range, the first verification pattern 8e, although not shown.

The positional relationship between 8d and the other side 9b of the second verification pattern 9 is the same as that in FIG. The resistance value between them becomes a predetermined value.

Next, if the overlay error between the actual base pattern and the desired mask pattern exceeds the allowable range, as shown in FIG.
When the side 9a is shifted in the direction of the verification pattern 8b, the side 9a overlaps the first verification pattern 8b, so that the side 9a and the first verification pattern 8b are electrically connected, and the side 9a is connected to the first verification pattern 8a.
If the other side 9b is deviated in the direction of the first verification pattern 8c or 8d, the side 9b and the first verification pattern 8a are electrically connected.
The verification pattern 8C or 8d is electrically connected.

Therefore, each of the first verification patterns 8a and 8b and the second
conduction/non-conduction with the side 9a of the verification pattern 9, and the first
The conduction/non-continuity between each of the verification patterns 8c and 8d and the side 9b of the second verification pattern 9 is measured, and if the results of these measurements are all non-conduction, the actual base pattern and the desired mask pattern are connected. It can be evaluated that the overlay error is within the allowable range, and if either of them is conductive, it can be evaluated that the overlay error between the actual base pattern and the desired mask pattern is beyond the allowable range, and which verification pattern is The direction of misalignment in overlay can be determined depending on whether there is continuity.

Moreover, both sides 9a of the second verification pattern 9 are prepared in advance.

The relationship between the resistance value of each of 9b and its line width is determined in advance, and as shown in FIG.
It is possible to derive the line widths of both sides 9a and 9b and quantitatively evaluate the line width of the actual mask pattern, but if the line width of the actual base pattern and mask pattern is larger than the standard dimension, the line width of the base pattern As the line width increases, the line width of each of the first verification patterns 8a to 8d increases, and the intervals between them conversely decrease.
As shown in FIG. 5, for example, the side 9a of the second verification pattern 9 overlaps the first verification patterns 8a and 8b and conducts between them, so that the side 9a (or 9b) and the first verification pattern 8a, 8b (or 8c, 8d), it can be seen that the line width of either the actual underlying pattern or the mask pattern is larger than the standard dimension.

Furthermore, in order to check whether the line width of the actual mask pattern is less than the standard dimension, for example, assuming that the tolerance range for the dimensional error of the actual mask pattern is ±0.1 μm, the actual dimension is the lower limit of the tolerance range. In order to check whether or not the line width of both sides 9a and 9b of the second verification pattern 9 is 0. If it is formed to have a thickness of 1 μm, as a result of examining the conduction between both ends of both sides 9a and 9b, for example, as shown in FIG.
If there is no conduction between both ends of the side 9b, or there is no conduction between both ends of the side 9b, it can be evaluated that the line width of the actual mask pattern is less than the standard dimension.

In this way, the conduction/non-conduction of both verification patterns 8a to 8d, 9 and the resistance values of both sides 9a, 9b of the second verification pattern 9 can be measured in a series of steps, so it is possible to evaluate overlay accuracy as in the conventional method. There is no need to perform the evaluation of the dimensional accuracy and the evaluation of dimensional accuracy in separate processes, and the evaluation process can be performed in a shorter time than conventionally, and the efficiency of the evaluation process can be improved.

In the above embodiment, the second verification pattern 9 is formed in a cross shape, but it may be formed in an L shape consisting of two orthogonal sides.

In addition, in the above embodiment, there are two types: the underlying pattern of the actual device and the mask pattern transferred to the resist above it.
Overlay accuracy of layer patterns.

Although the case where the dimensional accuracy is evaluated has been described, the present invention can be implemented in the same way even when evaluating a pattern with three or more layers. .

A method such as forming another verification pattern outside of 8b may be considered.

Furthermore, first verification patterns 8a, 8b (or 8c,
8d) with different intervals at a predetermined pitch, form a second verification pattern 9 for this pattern, and perform the above-mentioned evaluation to evaluate to what extent the overlay accuracy can be guaranteed. can also be done.

〔Effect of the invention〕

As described above, according to the method for evaluating overlay accuracy and dimensional accuracy of the present invention, the conduction/non-conduction of both verification patterns and the resistance value of the second verification pattern can be measured in a series of steps. The time required for evaluating overlay accuracy and dimensional accuracy can be reduced compared to the conventional method, which is extremely advantageous in manufacturing semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the overlay accuracy and dimensional accuracy evaluation method of the present invention, FIG. 2 is a sectional view taken along the line AA' in FIG. 1, and FIGS. a) is a partial plan view for explaining the evaluation procedure in Fig. 1, (b) of each figure is a cross-sectional view, and Fig. 7 (a) = (b) is an explanation of the conventional evaluation method of overlay accuracy. Plan view and cross-sectional view for Figure 8 (a
) and (b) are a plan view and a sectional view for explaining a conventional method for evaluating dimensional accuracy. In the figure, 88 to 8d are first verification patterns, 9 is a second verification pattern, and 9a and 9b are sides. In addition, it is shown.

Claims (1)

[Claims] (1) Overlay accuracy of a desired mask pattern transferred using photolithography to a photosensitive resin film formed on a conductive base pattern on a substrate and the base pattern, and the accuracy of the mask pattern. In the overlay accuracy and dimensional accuracy evaluation method for evaluating dimensional accuracy, a conductive first verification pattern is formed in the verification pattern formation area on the substrate by the same process as the base pattern, and the mask pattern and forming a conductive second verification pattern consisting of two orthogonal sides in the verification pattern formation area on the substrate using a monitor mask pattern formed in the same process; by positioning the first verification pattern on both sides of the base pattern and the mask, and measuring conduction/non-continuity between the first and second verification patterns and the resistance value of the second verification pattern. A method for evaluating overlay accuracy and dimensional accuracy, comprising evaluating overlay accuracy with a pattern and dimensional accuracy of the mask pattern.