JPH08162383A - Pattern for evaluating registration accuracy and evaluation method by use thereof - Google Patents

Abstract

PURPOSE: To provide a registration accuracy evaluating pattern which is capable of providing data related to registration accuracy high enough for fine processing of below sub-half micron and being observed by a SEM and an evaluation method by the use of the evaluating pattern. CONSTITUTION: A hole array is composed of square holes 4A to 4G which are arrayed deviating from each other by an optional space (s)in a direction (Y direction) along the rectilinear edge 2E of a lower pattern 2 but also by a constant deviation (d) in an X direction vertical to a Y direction, and the rectilinear edge 2E exposed inside the holes is observed by a length measuring SEM. The positions of the holes where the rectilinear edge 2E is observed inside them are compared with each other before and after a point where a deviation occurs in superposition, and the amount of superposition deviation is calculated by multiplying the shift number of the holes by a deviation (d). Hole arrays are arranged in two rows along both the edges of a wiring pattern, and a variation in line width is capable of being detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is for measuring the overlay accuracy of actual circuit patterns formed in each of a lower material layer and an upper material layer in a fine processing field such as a semiconductor manufacturing process. Regarding overlay accuracy evaluation pattern and evaluation method using the same, particularly with respect to a fine actual circuit pattern whose design rule is 0.5 μm or less, highly accurate overlay deviation detection by a scanning electron microscope, and further line width variation And a method that enables the detection of

[0002]

2. Description of the Related Art The design rule is being reduced with the miniaturization and high integration of semiconductor devices. In the next-generation 64M DRAM, which is about to be mass-produced, the minimum processing size is 0.35 μm or less, and the next-generation 256 MDRAM. Therefore, fine processing technology of 0.25 μm or less is required. This microfabrication technology has been directly supported by high resolution in photolithography and high anisotropy in dry etching.Along with these, on top of the actual circuit pattern on the lower layer, the actual circuit pattern on the upper layer is formed. Improving the overlay accuracy, which indicates how accurately the layers are superposed, is also an extremely important index that determines the success or failure of the semiconductor process.

A dedicated evaluation pattern is generally used to measure the overlay accuracy. This evaluation pattern is roughly classified into a vernier type and a box type. The vernier type pattern uses the fact that when the lower layer pattern and the upper layer pattern, in which predetermined figures are arranged at different pitches, are overlapped, the overlapping condition of both figures changes depending on the location, and there is a misalignment of the superposition. It can be detected. The reading of this deviation is usually performed using an optical microscope. On the other hand, the box-type pattern is a lower layer pattern formed as a square opening, and an upper layer pattern of a smaller square is superposed on the lower layer pattern. The overlay deviation is detected by comparing the distances along the four sides. This detection is usually
It is automatically performed using the alignment optical system of the stepper.

[0004]

However, with the conventional evaluation pattern or evaluation method, it is not always easy to accurately determine a minute overlay deviation. For example, in the case of a vernier scale type evaluation pattern, since the deviation is read with an optical microscope, it is sufficient for a process in which the minimum processing dimension is on the level of half micron or sub-half micron because of the resolution limit. Inaccurate measurements cannot be made.

On the other hand, when the box type evaluation pattern is used, the diffracted light is automatically analyzed by the alignment optical system, so that the evaluation accuracy is improved as compared with the case where the vernier type evaluation pattern is used. To do. However, if the monochromatic light used for the measurement is strong, the intensity of the diffracted light is extremely reduced due to interference, which may make the measurement extremely difficult. Further, generally, unless the evaluation pattern is arranged in the immediate vicinity of the pattern to be evaluated, it is impossible to obtain information faithful to the change occurring in the pattern. This is because the direction of misalignment caused by photolithography is not uniform within the exposure area of one shot due to the aberration of the projection lens and the like. However, the box-type evaluation pattern is as large as several tens of μm on a side, and the place where it can be formed in the chip is limited. Therefore, this pattern is the actual circuit pattern in the chip to be evaluated or the TE to be evaluated.
It cannot always be placed in the immediate vicinity of G (test element group).

By the way, a scanning electron microscope for length measurement (length measurement SEM) is widely used for measuring planar dimensions such as line width and hole diameter in recent semiconductor processes, and also for measuring overlay accuracy. It is believed that the excellent resolution of SEM is available. However, observing the existing evaluation pattern as it is with the SEM is restricted by the following reasons. First, in the length measurement SEM, since the image of secondary electrons generated from the surface of the sample irradiated with the electron beam is observed, the sample does not have a surface structure that rapidly changes the incident angle of the electron beam, that is, no step. in case of,
A clear image cannot be obtained. For example, in the case of the above-mentioned box-type evaluation pattern, the position of the lower layer pattern should be accurately determined if the lower layer pattern has a large square edge and the step is reduced or the edge becomes dull due to the coating of the upper layer material layer. Therefore, overlay accuracy with the upper layer pattern cannot be accurately evaluated. In addition, when it is desired to evaluate the overlay accuracy of the hole pattern with respect to the lower layer wiring pattern, if the optical measurement method is used, even if the lower layer wiring pattern remains covered with the interlayer insulating film, the interlayer insulating film is transparent. I was able to observe the edge of the lower layer wiring pattern through
This cannot be done with SEM.

Therefore, the present invention can provide information on overlay accuracy with sufficient accuracy for sub-half micron or later microfabrication processes, and an overlay accuracy evaluation pattern suitable for SEM measurement and this It is an object of the present invention to provide an evaluation method capable of measuring overlay deviation with high accuracy.

[0008]

The present invention is proposed to achieve the above object. First, the overlay accuracy evaluation pattern of the present invention is such that the lower layer pattern formed by using the lower layer material layer on the substrate and the upper layer pattern formed by using the upper layer material layer that covers the lower layer pattern overlap each other. Providing information on the overlay accuracy of the actual circuit patterns formed on each of the lower layer material layer and the upper layer material layer based on the state, wherein the upper layer pattern is a straight line of the lower layer pattern. It is composed of a plurality of holes that are arranged at arbitrary intervals in the direction along the edge, are arranged with a certain amount of deviation in the direction perpendicular to the straight edge, and have at least the same dimension in the direction perpendicular to the straight edge. At least one row of hole arrays is provided, and the lower layer patterns of different areas are exposed on the bottom surface of each hole. For such holes, first, a resist pattern according to the hole pattern is formed on the upper layer material layer, and this resist pattern is used as a mask, and the upper layer is formed under the condition that a sufficient selection ratio is obtained with respect to the lower layer pattern. It is formed by anisotropically etching the side material layer.

By the way, generally, in the semiconductor process, the minimum processing dimension is applied to the gate electrode of the MOS transistor and the connection holes (holes) such as contact holes and via holes. The minimum processing size may not be applied. In the present invention, the part where the specific numerical value should be defined is only the above-mentioned deviation amount, which is related to the evaluation accuracy. In the present invention, if the fixed amount of deviation is set to ⅕ or less of the minimum processing dimension applied to the formation of the actual circuit pattern, the evaluation can be performed with a practically acceptable accuracy.
For example, when the minimum processing dimension is 0.25 μm, the deviation amount is 0.05 μm or less. The measurable range of the overlay deviation in the present invention is (the number of holes in one row of hole array-1) x the amount of deviation. Therefore, the number of holes can be appropriately determined in consideration of the process accuracy. good.

The hole array may be provided in a plurality of columns. For example, when the lower layer pattern is a linear strip having a predetermined line width, if the hole arrays are arranged in two rows along the left and right straight edges of the linear strip, not only the information about the overlay misalignment but also It is also possible to obtain information on line width variations. If the pitch of the two rows of hole arrays, that is, the distance between the centers of the left and right holes is set equal to the design line width of the linear strip, the position of the hole in which the straight edge is observed in the center is left and right. The line width variation and overlay misalignment can be easily evaluated.

By the way, when forming the lower layer pattern and the upper layer pattern in the overlay accuracy evaluation pattern of the present invention, naturally, the actual circuit pattern is also formed in other regions, but it is formed by processing the lower layer side material layer. In theory, the lower layer pattern and the actual circuit pattern, or the upper layer pattern formed by processing the upper layer side material layer and the actual circuit pattern do not necessarily need to have commonality. As an extreme example, when processing the upper material layer, for example, a process of resolving the wiring pattern in the formation region of the actual circuit pattern and resolving the hole pattern in the formation region of the evaluation pattern is performed. It may be. However, since the exposure conditions of photolithography are generally quite different between the wiring pattern and the hole pattern, it is better in practice to have some commonality between the actual circuit pattern and the evaluation pattern. Therefore, it is particularly preferable that the lower layer pattern imitates the wiring pattern in the circuit pattern and the upper layer pattern imitates the connection hole pattern in the circuit pattern.

On the other hand, in the evaluation method of the present invention, the overlay accuracy of the circuit patterns formed on each of the lower layer side material layer and the upper layer side material layer is checked by using any of the above-described overlay accuracy evaluation patterns. A method for evaluating, comparing the position in the hole array of holes observed with the straight edge of the lower layer pattern as the center, before and after the occurrence of overlay misalignment between the circuit patterns, and separating the positions The number of holes shown is multiplied by the above-mentioned constant deviation amount to obtain the overlay deviation.

Further, in particular, the hole array has two rows along the left and right straight edges of the straight strip, and
When using an evaluation pattern in which the distance between the row hole arrays is set equal to the design line width of the linear strip, the intermediate position of the left and right holes is set to the straight edge of the lower layer pattern before the misalignment occurs. Is compared with the reference position in the hole array of the hole observed at the center, and the number of holes representing the distance between these two positions may be multiplied by the predetermined deviation amount. At this time, the intermediate position between the left and right holes comes on the hole if the number of holes existing between the holes is odd, and between the holes if the number of holes is even. In other words, the distance between the two positions can be expressed in 0.5 increments. Therefore, the evaluation accuracy in this case is half the deviation amount between the individual holes. The method of obtaining the overlay deviation can be performed by excluding the factor of the line width variation.

In order to check whether or not the line width variation is occurring, the position of the hole observed around the straight edge of the lower layer pattern is observed in each of the left and right two-row hole arrays. The number of holes representing the distance between the left and right holes may be multiplied by the fixed amount of deviation. In principle, the above observation can be performed using an AFM (atomic force microscope) or STM (scanning tunneling electron microscope), but it can be most easily performed using an SEM.

[0015]

In the overlay accuracy evaluation pattern of the present invention, since the lower layer patterns having different areas are exposed on the bottom surface of each hole in the row of holes array, the holes are separated from the lower layer pattern. Unless completely offset or completely overlapped, a step due to the straight edge of the lower layer pattern is formed on the bottom surface of the hole. Therefore, the misalignment can be evaluated accurately and easily by an observation method such as SEM that detects the secondary electrons emitted from the sample surface. Although it is difficult to judge whether or not the straight edge passes through the center of the hole by observing only one hole, in the hole array in which a plurality of holes are arranged with a certain amount of deviation as described above. In that case, the tendency of the deviation can be grasped by observing other holes together, which facilitates the determination. This overlay accuracy evaluation pattern is (design line width + α) even when two rows of hole arrays are provided.
Since it can be formed in a space having a certain width, it can be arranged with a relatively high degree of freedom in the vicinity of the actual circuit pattern or TEG to be observed. This also contributes to the improvement of evaluation accuracy.

Since the overlay misalignment is observed in the direction perpendicular to the straight line edge of the lower layer pattern, if one knows how many holes the position of the hole observed around this straight line edge is shifted from the design time. The absolute value of the overlay deviation can be obtained as the product of the number of holes and the deviation amount of each hole. In this case, the amount of deviation between individual holes is the evaluation accuracy.

Further, when two rows of hole arrays are provided at a pitch equal to the designed line width, the positional deviation of the left and right holes due to the fluctuation of the line width does not occur if the misalignment does not occur. The same magnitude occurs in the opposite direction with respect to the center, but when the overlay deviation occurs, the magnitude of the deviation in the opposite direction also differs from each other. Therefore,
If you find the middle position of the left and right holes observed with the straight edge as the center and know the center of the deviation in the opposite direction, and know how many holes the center of this deviation has shifted from the reference position at the time of design, The absolute value of the overlay deviation can be obtained as the product of the number of holes and the deviation amount of each hole. In this case, half of the deviation amount of each hole is the evaluation accuracy.

If there is no variation in the line width of the lower layer pattern, the holes observed with the straight edge of the lower layer pattern at the center are located at the same reference position in both arrays, that is, on the same vertical line with respect to the straight edge. is there. However, when a line width variation occurs, the position of the hole observed around the straight edge shifts left and right depending on the magnitude of the variation and the direction of the variation (ie, enlargement or reduction). Therefore, by knowing how many holes are separated from each other on the left and right, the absolute value of the line width variation can be obtained as a product of the number of holes and the deviation amount of each hole. In this case, the amount of deviation between individual holes is the evaluation accuracy.

[0019]

EXAMPLES Specific examples of the present invention will be described below. Example 1 In this example, an overlay accuracy evaluation pattern used when overlaying a hole pattern on a lower layer pattern having a straight edge in a part of the pattern and an evaluation method using the overlay pattern will be described with reference to FIG. explain.

This overlay accuracy evaluation pattern includes a lower layer pattern 2 formed by processing the lower layer side material layer on the substrate 1, and seven square holes 4A, 4B formed in the upper side material layer 3. The overlay accuracy is evaluated based on the degree of overlap with the upper layer pattern composed of 4C, 4D, 4E, 4F, and 4G. Here, the lower material layer is typically a conductive material film such as a polysilicon film, an aluminum-based multilayer film, or a polycide film, and is a film for forming a wiring pattern as an actual circuit pattern. The upper material layer 3 is an insulating film made of a silicon oxide film, a silicon nitride film, or the like, and an actual circuit pattern is a film that serves as an interlayer insulating film for opening a contact hole such as a contact hole or a via hole.

The seven holes 4A to 4G are straight edges 2E as can be seen from the top view shown in the right half of FIG.
Are arranged with a predetermined gap s in the direction (Y direction) and with a constant deviation amount d in the direction (X direction) perpendicular to the straight edge 2E. The hole 4A is completely off the lower layer pattern 2, and the hole 4G is completely overlapped with the lower layer pattern 2. Other Halls 4B-4F
The lower layer pattern 2 having an area corresponding to the degree of overlap is exposed on the bottom surface of the. That is, these holes 4B-4
As can be seen from the Y direction sectional view of each hole shown in the left half of FIG. 1, a step of a straight edge 2E is formed inside F so that it can be easily observed by SEM.

Generally speaking, the holes are the portions to which the minimum processing size is applied in the actual circuit pattern of the semiconductor integrated circuit, but the size Wh of the above-mentioned seven holes 4A to 4G.
The minimum processing size does not necessarily have to be applied to (length of one side). Further, although the shape of each hole is a square here, it may be a rectangle having an arbitrary aspect ratio. However, only the length in the X direction must be exactly the same in every hole. If they do not match, it is not possible to determine whether or not the straight edge 2E passes through the center of the hole. Further, the space s between the holes is not necessarily the one to which the minimum processing size should be applied. Further, although the space s between the holes is constant here, it may be different.

On the other hand, the deviation amount d in the Y direction of each hole is the most important amount that determines the evaluation accuracy in the present invention.
In the present invention, the overlay deviation is determined based on the shift of the position of the hole observed with the straight edge 2E as the center, as will be described later. Therefore, this deviation amount d needs to be accurately matched between the holes. . The absolute value of the deviation amount d is selected to be 1/5 or less of the minimum processing dimension.

Since the width in the X direction of the space required for the formation of such an overlay evaluation pattern is slightly d × (number of holes-1) + Wh, it should be placed near the actual circuit pattern or TEG to be measured. This enables highly accurate evaluation.

Next, an evaluation method using this overlay accuracy evaluation pattern will be described. First, it is assumed that the evaluation pattern is designed so that the straight edge 5E of the lower layer pattern 5 can be seen at the center of the hole 4C when the overlay deviation has not occurred. The position of hole 4C is
This is the third hole from the top in this hole array and is defined as the reference hole. However, in actuality, the overlay deviation of the upper layer pattern occurred, and the hole observed centering on the straight edge 2E of the lower layer pattern 2 was shifted to the fourth hole 4D from the top. That is, the shift of the hole position from the reference hole is 1 (= 4-3) holes. Therefore, the overlay deviation in this case is d from d × (4-3) = d.

When it is difficult to determine the hole observed with the straight edge 2E as the center, the lower layer pattern 2 is formed inside.
Is not visible at all, and it is determined to be hole 4D (4th hole) by taking the middle of hole 4A (1st hole) and hole 4G (7th hole) where lower layer pattern 2 is visible on the entire surface. You can also Second Embodiment In the first embodiment described above, the fluctuation of the overlay under the ideal condition where there is no fluctuation of the line width of the lower layer pattern was discussed, but in the actual process, the fluctuation of the line width often occurs. In view of this, in this embodiment, a hole array is arranged in two rows, and in addition to the overlay deviation between the wiring pattern and the holes, an overlay accuracy evaluation pattern that enables simultaneous detection of line width variations, and an evaluation method using this This will be described with reference to FIGS. 2 to 4.

As shown in FIG. 2, the evaluation pattern of this embodiment has a left-right two-row hole array, and the left-hand hole array has eleven holes 11L to 21L (subscript L is the left-hand hole. The hole array on the right is 11 holes 11R to 21R.
(The subscript R indicates that it is a member of the hole array on the right side). These holes 11L-21
L, 11R to 21R all have dimensions (length of one side) Wh
, And are arranged in each hole array with a constant displacement amount d, as in the first embodiment. The pitch of the left and right hole arrays (the distance between the centers of the left and right holes along the X direction) is the design value W of the wiring pattern 30 on the lower layer side.
p ₁ and any holes in each hole array are aligned left and right in the Y direction. For example, the hole 13L and the hole 13R are at the same position in the Y direction. Here, as an example, the hole dimension Wh = 0.
5 μm, deviation amount d = 0.1 μm, design line width Wp ₁ = 1.
Set to 5 μm.

In the ideal state as shown in FIG. 2, that is, in the case where neither overlay misalignment nor line width variation occurs, the holes observed around the edge 30E of the wiring pattern 30 are 16L and 16R. Both are 6th from the top in the hole array. The positions of these holes are referred to as reference position A. Here, since the distance between the left and right hole arrays is matched with the line width Wp ₁ of the wiring pattern 30, the reference positions A are thus aligned in the Y direction on the left and right.

Next, an evaluation method in the case where there is no overlay deviation and only line width variation occurs will be described with reference to FIG. Here, as a result of the line width of the wiring pattern 30 widening to become the wiring pattern 40, the holes observed centering on the edge 40E are 13 holes in the left hole array.
L, shifted to 19R in the right hole array. The positions of these holes 13L and 19R are a
_{Let L} and a _R. Here, the intermediate position b between a _L and a _R coincides with the reference position A. This means that the point where the center of the wiring pattern and the midpoint between the left and right holes match did not change. In other words, the shift of the holes occurs vertically symmetrically with respect to the reference position A because the overlay deviation does not occur. Where the positions a _L , a
The distance between _Rs is 6 (= 19−13) holes. Therefore, the variation amount of the line width in this case is d × (19−13) = 0.1 × 6 = 0.6 (μm). Therefore, the line width of the wiring pattern 40 is (designed line width) + ( It can be seen that the line width variation amount) = 1.5 + 0.6 = 2.1 (μm).

Next, an evaluation method in the case where both overlay misalignment and line width variation occur will be described with reference to FIG. Here, as a result of the line width of the wiring pattern 30 widening to become the wiring pattern 50 and the line width changes, the hole observed around the edge 50E is the left hole.
Shifted to 14L in the array and 20R in the right hole array. The positions of these holes 14L and 20R are a _L and a _R , respectively. Moreover, a _L , a _R
The intermediate position b between and does not match the reference position A. This means that the point where the center of the wiring pattern and the midpoint between the left and right holes coincide has changed. In other words,
Due to the misalignment, the holes are shifted vertically asymmetrically with respect to the reference position A. The distance between the positions a _L and a _R is 6 (= 20-
14) The quantity. Therefore, the line width variation amount in this case is d × (20−14) = 0.1 × 6 = 0.6 (μm), and thus the line width of the wiring pattern 50 is 2.1 μm.
It turns out that it is m.

On the other hand, the intermediate position b between the positions a _L and a _R is shifted from the reference position A by one hole (= 17-16). Therefore, it can be seen that the overlay deviation is d × (17−16) = 0.1 × 1 = 0.1 (μm). In other words, this method can also be said to be a method capable of evaluating the overlay accuracy by excluding the factors of line width variation.

In the case of the present embodiment, the distance between the intermediate position b and the reference position A can be known in the order of 0.5 holes. For example, the position a _L ,
If the distance between a _R is not the even number (6) as described above in terms of the number of holes but an odd number such as 5 for example, the intermediate position b is between the holes. , And the number of holes is calculated to be 2.5. Therefore, the evaluation accuracy of this embodiment is 0.05 μm, which is a half of the deviation amount d.

In this embodiment, only the case where the line width of the wiring pattern is expanded has been described. However, in the case of contraction, the direction of hole shift is only opposite, and the same evaluation is possible. In other words, the hole observed at the edge of the wiring pattern is the hole on the left side as the line width shrinks.
In the array shifts to higher numbered holes than 16L and to the right side hole array shifts to lower numbered holes than 16R.

The present invention has been described above based on the two embodiments, but the present invention is not limited to these embodiments. For example, the shape of the holes, the number of holes forming one row of the hole array, the hole size, the hole shape, the distance between the holes, the deviation amount, etc. can be changed according to the desired evaluation accuracy. Further, by disposing a plurality of hole arrays along each side of the polygonal pattern, it is possible to evaluate the occurrence of overlay misalignment along any direction.

[0035]

As is apparent from the above description, according to the present invention, a hole pattern is superposed on a wiring pattern of a semiconductor device manufactured based on a sub-half micron or finer design rule. Also in the case of alignment, it becomes possible to evaluate overlay with extremely high accuracy using SEM. Therefore, the present invention greatly contributes to miniaturization, high integration, and high performance of semiconductor devices through improvement of accuracy in evaluation of overlay accuracy.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration example of an overlay accuracy evaluation pattern in which a row of hole arrays are arranged along a straight edge portion of a lower layer pattern.

FIG. 2 is a plan view showing a case where neither overlay misalignment nor line width variation of the wiring pattern occurs in the overlay accuracy evaluation pattern in which two rows of hole arrays are arranged along the left and right edges of the wiring pattern. is there.

FIG. 3 is a plan view showing a state in which there is no overlay deviation in FIG. 2 and only line width variation occurs.

FIG. 4 is a plan view showing a state in which both overlay misalignment and line width variation in FIG. 2 have occurred.

[Explanation of symbols]

 2 Lower layer pattern 2E Straight edge (of lower layer pattern) 3 Upper layer side material layer 4A to 4G, 11L to 21L, 11R to 21R Hole 30, 40, 50 Wiring pattern 30E, 40E, 50E Edge of wiring pattern d Shift amount Wh Hole dimensions (length of one side)

Claims (9)

[Claims] 1. The lower layer based on the overlapping state of the lower layer pattern formed by using the lower layer material layer on the substrate and the upper layer pattern formed by using the upper layer material layer covering the lower layer pattern. A overlay accuracy evaluation pattern that provides information about overlay accuracy between actual circuit patterns formed on each of the side material layer and the upper side material layer, wherein the upper layer pattern is along a straight edge of the lower layer pattern. Are arranged at arbitrary intervals in the direction, and are arranged with a certain amount of deviation in the direction perpendicular to the straight edge,
And having at least one row of hole arrays composed of a plurality of holes having at least the same dimension in the direction perpendicular to the straight edges, and exposing the lower layer patterns of different areas on the bottom surface of each hole. Overlay accuracy evaluation pattern. 2. The overlay accuracy evaluation pattern according to claim 1, wherein the constant deviation amount is not more than ⅕ of a minimum processing dimension applied to the formation of the actual circuit pattern. 3. The lower layer pattern has linear strip portions having a predetermined line width, and the hole arrays are arranged in two rows along the left and right straight edges of the linear strip portions.
Alternatively, the overlay accuracy evaluation pattern according to claim 2. 4. The overlay accuracy evaluation pattern according to claim 3, wherein the pitch of the two rows of hole arrays is equal to the design line width of the linear strip. 5. The lower layer pattern imitates a wiring pattern in the actual circuit pattern, and the upper layer pattern imitates a connection hole pattern in the actual circuit pattern. The described overlay accuracy evaluation pattern. 6. An actual circuit pattern formed between each of the lower layer side material layer and the upper layer side material layer using the overlay accuracy evaluation pattern according to any one of claims 1 to 5. An evaluation method for evaluating overlay accuracy, wherein the positions in the hole array of holes observed with a straight edge of the lower layer pattern as a center are compared before and after occurrence of overlay misalignment between the actual circuit patterns. An evaluation method for obtaining an overlay deviation by multiplying the number of holes representing the distance between both positions by the constant deviation amount. 7. The overlay accuracy of the actual circuit patterns formed on each of the lower layer side material layer and the upper layer side material layer is evaluated by using the overlay accuracy evaluation pattern according to claim 4 or 5. In the evaluation method, the middle positions of the left and right holes are compared with a reference position in the hole array of holes in which a straight edge of the lower layer pattern is observed in the center before a misalignment occurs, and both positions are compared. An evaluation method for obtaining the overlay deviation by multiplying the number of holes, which represents the distance, by the constant deviation amount. 8. In each of the left and right two-row hole arrays, the position of holes observed with a straight edge of the lower layer pattern as a center is observed, and the fixed deviation is made to the number of holes representing the distance between the left and right holes. The evaluation method according to claim 7, wherein the line width variation is obtained by multiplying the amount. 9. The evaluation method according to claim 6, wherein the observation is performed using a scanning electron microscope.