JPH01312868A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To assure an ohmic contact between a barrier metal and a P type diffusion layer by ion-implanting a P type impurity into the P type diffusion layer and forming a highly concentrated diffusion layer only on the surface of the P type diffusion layer. CONSTITUTION:An N type diffusion layer 14, a P type diffusion layer 15, and an interlayer insulating film 20 are formed on a silicon substrate 11, and contact holes 21, 22 are formed through the interlayer insulating film. After the contact hole 22 is formed, a resist layer 23 is formed only on the P type diffusion layer 15, and the P type diffusion layer 15 is ion-implanted with a P type impurity using a pattern of the resist layer 23 as a mask to increase surface concentration of the P type diffusion layer 15 for formation of a high concentration diffusion layer 24. Accordingly, a barrier metal process is usable as it is as a conventional process, without influence thereof onto a P type transistor. Thus, an ohmic contact is assured between the barrier metal and the P type diffusion layer.

Description

[Detailed Description of the Invention] [Summary of the Invention] In a semiconductor device having a CMOS structure, barrier metal and P
Regarding a method of manufacturing a semiconductor device that obtains ohmic contact with a type diffusion layer, the present invention aims to provide a method of manufacturing a semiconductor device that can make low ohmic contact with a P type diffusion layer when using a barrier metal. In a semiconductor device having a CMOS structure, a step of forming a contact hole in a silicon substrate, an N-type diffusion layer, a P-type diffusion layer, a glabellar insulating film, and a glabellar insulating film, and a contact of the glabellar insulating film on the P-type diffusion layer. a step of forming a resist film with a pattern in which only holes are opened; and a step of ion-implanting P-type impurities using the resist film as a mask and forming a highly concentrated diffusion layer on the surface of the P-type diffusion layer by annealing. and forming a wiring layer having a barrier metal in the contact hole.

[Industrial application field]

The present invention is based on CMO3 (Complementary M
The present invention relates to a method for manufacturing a semiconductor device that obtains ohmic contact between a barrier metal and a P-type diffusion layer in a semiconductor device having a metal oxide semiconductor structure.

[Prior Art] Conventionally, approximately 1 to 2% by weight of silicon (Af) is mixed in aluminum (Af) for wiring of large-scale integrated circuits (LSI).
An aluminum-silicon (Affi-3i) alloy containing Si) was used. However, with the miniaturization of devices, the contact holes (or pier holes: Via holes) that make electrical contact between the wiring and the substrate have become miniaturized, and contact holes of 1.0 μm or less are now required. Therefore, when a conventional ^1-3t alloy is used as a wiring material in a device using these contact holes, A I! , -5i is epitaxially grown (solid phase epitaxial growth), resulting in a problem of increased contact resistance. Therefore, it is necessary to suppress solid phase epitaxial growth using a barrier metal, but the current CMO3
type semiconductor device, if it is directly introduced into the manufacturing process, there are problems such as the contact with the P type diffusion layer not being an ohmic contact or the contact resistance becoming high.

[Problems to be Solved by the Invention] Therefore, barrier metal technology cannot be directly introduced into current semiconductor manufacturing processes.

In order to obtain ohmic contact with the P-type diffusion layer, increasing the dose of ion implantation during the formation of the P-type diffusion layer may change the characteristics of the P-channel transistor or cause problems in miniaturized semiconductor devices. A problem arises in that the P-channel transistor becomes a short channel.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that allows low ohmic contact with a P-type diffusion layer when using a barrier metal.

[Means to solve problems]

The above problem is that in a semiconductor device with a CMO5 structure, an N-type diffusion layer, a 1) type diffusion layer, an interlayer insulating film,
a step of forming a contact hole in the interlayer insulating film, a step of forming a resist film with a pattern in which only the contact hole of the interlayer insulating film on the P-type diffusion layer is opened, and a step of forming a P-type impurity using the resist film as a mask. ion implantation,
A method for manufacturing a semiconductor device, comprising the steps of: forming a high concentration diffusion layer on the surface of the P-type diffusion layer by annealing; and forming a wiring layer containing a barrier metal in the contact hole. solved by.

FIG. 1 is a cross-sectional view of a semiconductor device at an intermediate step to explain the present invention in detail. In the figure, 11 is a silicon substrate, 12 is a P-well, 13 is an N-well, 14 is an N-type diffusion layer formed in the P-well 12, 15 is a P-type diffusion layer formed in the N-well 13, and 16 is a selection. Oxidation method (LOCOS)
element isolation region of silicon oxide film formed by
17 is a gate oxide film, 18 is a gate electrode of an N-type transistor formed on the gate oxide film 17, 19 is a gate electrode of a P-type transistor formed on the gate oxide film 17, and 20 is a glabellar insulation made of PSG or the like. 21 is a contact hole on the N-type transistor side, 22 is a contact hole on the P-type transistor side, and 23 is a resist film with a pattern opening only on the P-type diffusion layer 15. Using the pattern of this resist film 23 as a mask, , P-type impurities are ion-implanted, and only the surface of the P-type diffusion layer 15 is made into a highly concentrated diffusion layer 24.
shall be.

(Function) In the present invention, after opening the contact hole 22, the resist layer 23 is opened only on the P-type diffusion layer 15, and P-type impurities are ion-implanted using the pattern of the resist film 23 as a mask. The surface concentration is increased to form a high concentration diffusion layer 24. Therefore, there is no effect on the P-type transistor, and the barrier metal process can be used as is the conventional process.

〔Example〕

Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.

FIGS. 2(a) to 2(d) are sectional views showing the manufacturing process of a CMOS structure semiconductor device according to an embodiment of the present invention. Note that parts corresponding to those in FIG. 1 are indicated by the same symbols.

First, as shown in FIG. 2(a), a P well 12 and an N well 13 are formed in a silicon substrate 11 by ion implantation or the like using a conventional method. And LOC
An element isolation region 16 is formed by O3 method, and a P well 12 is formed.
After forming a thin gate oxide film 17 on the surface of the N well 13 and depositing a polysilicon film on the entire surface, a gate/electrode 18 of N type MO3 and a gate electrode 19 of P type MO5 are formed by patterning. Next, by ion implantation etc., N type and P type? An N-type diffusion layer 14 and a P-type diffusion layer 15 for source/drain regions of lO5 are formed.

Next, as shown in the same figure (1)), phosphorus glass (PSG)
After depositing an interlayer insulating film 20 made of the like on the entire surface, contact holes 21 and 22 are opened.

Next, as shown in the same figure (C), a resist film 23 is applied to form a resist film 23 with an opening only in the upper part of the P-type diffusion layer 15, and B' ions or BF2'' ions are added as P-type impurities. , 40keV, dose 4
Inject at about xl, 014-2 x20I5cm-2. Then, at 900°C in a nitrogen (N2) gas atmosphere.
Activation annealing is performed for about 515 minutes to form the P-type diffusion layer 15.
A high concentration diffusion layer 24 with an increased surface concentration is formed.

Next, as shown in FIG. 3(d), after removing the resist film 23, for example, titanium (Ti) is deposited by sputtering or the like.
) is deposited on the entire surface, and after depositing a wiring metal 26 such as H2 alloy on the barrier metal 24, a wiring layer is formed by predetermined patterning.

According to the above manufacturing method, the resist film 23 is formed in a pattern with an opening only in the upper part of the P-type diffusion layer 15, and the P-type impurity is ion-implanted to increase the surface concentration of the P-type diffusion layer 15. A diffusion layer 24 can be formed.

In particular, a shallow impurity diffusion layer is formed by BF2'' ion implantation. Therefore, since the surface concentration of the P-type diffusion layer 15 becomes sufficiently high, the P-type diffusion layer 15 and the barrier metal 25
can make ohmic contact. In addition, since ions are selectively implanted only into the contact hole 22 opened on the surface of the P-type diffusion layer 15, a contact formation technique using the barrier metal 25 is introduced without changing the characteristics of the conventional P-type MO3. It becomes possible to
The contact holes 21 and 22 can be miniaturized.

In the above embodiment, the barrier metal 25 is formed by a sputtering method, but the contact hole 22 may be filled with metal by a selective CVD method.
Silicides such as tungsten (W) and titanium (Ti),
A pure metal with a high melting point or the like can be used.

〔Effect of the invention〕

As explained above, according to the present invention, in order to lower the contact resistance with the P-type diffusion layer, after opening the contact hole, P-type impurity is ion-implanted into the P-type diffusion layer, and only the surface of the P-type diffusion layer is implanted. Since a highly concentrated diffusion layer is formed in the layer, an ohmink contact can be obtained between the barrier metal and the P-type diffusion layer, and ions can be selectively implanted only into the contact hole opened on the surface of the P-type diffusion layer. Therefore, it is possible to introduce contact formation technology using barrier metal without changing the characteristics of conventional P-type transistors, achieving miniaturization of contact holes, and increasing the degree of integration of such CMO5 type semiconductor devices. It greatly contributes to improvement.

[Brief explanation of the drawing]

Fig. 1 is a sectional view explaining the present invention in detail, Fig. 2(a)
-(d) are sectional views showing the manufacturing process of the embodiment of the present invention. In the figure, 11 is a silicon substrate, 12 is a P well, 13 is an N well, 14 is an N type diffusion layer, 15 is a P type diffusion layer, 16 is an element isolation region, 17 is a gate oxide film, 18 and 19 are gate electrodes. , 20 is an insulating film between the eyebrows, 21 and 22 are contact holes, 23 is a resist film, 24 is a high concentration diffusion layer 25 as a barrier metal, and 26 is a wiring metal. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akido Kukimoto Yoshiyuki Osuga

Claims (1)

[Claims] In a semiconductor device having a CMOS structure, a silicon substrate (
11), an N-type diffusion layer (14), a P-type diffusion layer (15),
An interlayer insulating film (20), a step of forming contact holes (21, 22) in the interlayer insulating film (20), and only contact holes (22) in the interlayer insulating film (20) on the P-type diffusion layer (15). forming a resist film (23) with an opening pattern; using the resist film (23) as a mask, ion-implanting a P-type impurity, and annealing the P-type diffusion layer (15);
a step of forming a high concentration diffusion layer (24) on the surface of the semiconductor; and a step of forming a wiring layer having a barrier metal (25) in the contact hole (21, 22). Method of manufacturing the device.