JPS6336555A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6336555A JPS6336555A JP61178637A JP17863786A JPS6336555A JP S6336555 A JPS6336555 A JP S6336555A JP 61178637 A JP61178637 A JP 61178637A JP 17863786 A JP17863786 A JP 17863786A JP S6336555 A JPS6336555 A JP S6336555A
- Authority
- JP
- Japan
- Prior art keywords
- type
- diffusion region
- diffused region
- type diffusion
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 230000002093 peripheral effect Effects 0.000 claims abstract 2
- 238000009792 diffusion process Methods 0.000 claims description 38
- 230000003213 activating effect Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- -1 BF227 ions Chemical class 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特にバリアメタルを用い九コンタ
クトを有する０ＭＯ８の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a method for manufacturing an OMO8 having nine contacts using a barrier metal.
従来、浅い接合及び微小コンタクトを有する０ＭＯ８に
おいて、ＡＩ −Ｓ ｉ等のＡｌ系配線からのＡｌス・
９イク等による不純物拡散領域の突き抜は及び３ｉ析出
によるコンタクト抵抗増加を防ぐ為に、コンタクトでは
例えばＡＪ−８ｔ／Ｔｉ−Ｗのバリアメタル構造を用い
ていた。以下、第２図に基き従来例を説明する。Conventionally, in OMO8 with shallow junctions and minute contacts, Al traces from Al-based interconnects such as AI-Si
In order to prevent penetration of the impurity diffusion region by 9-iron etching and an increase in contact resistance due to 3i precipitation, a barrier metal structure of AJ-8t/Ti-W, for example, was used for the contact. Hereinafter, a conventional example will be explained based on FIG.
まず、Ｎ型シリコン基板１１にＰウェル１２及びＮウェ
ル１３を夫々形成し、次に素子分離工程を経てフィール
ド酸化膜１４を形成することによシ基板をアクティブ領
域１１ａとフィールド領域１１ｂとに分離する。次いで
、夫々のアクティブ領域１１ａ上にゲート酸化膜１５及
びポリクリコンｒ−）電極（Ｎ型）１６を形成する。First, a P well 12 and an N well 13 are formed on an N-type silicon substrate 11, and then a field oxide film 14 is formed through an element isolation process to separate the substrate into an active region 11a and a field region 11b. do. Next, a gate oxide film 15 and a polycone r-) electrode (N type) 16 are formed on each active region 11a.
しかる後、ｆ−）絶縁膜１５及びポリシリコンゲート電
極１６をマスクとして、基板にＮ型不純物及び２世不純
物のイオン注入を行い、夫々のアクティブ領域１１ａに
？型拡散領域１７及びＰ＋型拡散領域１８を形成する。After that, f-) Using the insulating film 15 and the polysilicon gate electrode 16 as a mask, ions of N-type impurities and second-generation impurities are implanted into the substrate into each active region 11a. A type diffusion region 17 and a P+ type diffusion region 18 are formed.
次に中間絶縁膜２０を積層し、更に各拡散領域１７．１
８及びポリシリコンゲート電極１６上に、夫々コンタク
トホール２１を形成する。この後、バリアメタル２２及
びＡｊ層２３から成るバリアメタル構造の配線層２４を
形成し、同一基板にＮＭＯＳ ２５とＰＭＯＳ２６とを
作シ込む。Next, the intermediate insulating film 20 is laminated, and each diffusion region 17.1 is further laminated.
Contact holes 21 are formed on the polysilicon gate electrode 8 and the polysilicon gate electrode 16, respectively. Thereafter, a wiring layer 24 having a barrier metal structure consisting of a barrier metal 22 and an Aj layer 23 is formed, and an NMOS 25 and a PMOS 26 are formed on the same substrate.
しかしながら、上述した従来のコンタクト構造では、０
ＭＯ８の場合、Ｐ型拡散領域上コンタクトにおいてはＳ
ｌが析出し易いことと相まって、コンタクト径が１１１
ｍ口程度になると、コンタクト抵抗が数に９７個と非常
に高くなってしまうという問題があった。However, in the conventional contact structure described above, 0
In the case of MO8, in the contact on the P type diffusion region, S
Coupled with the fact that l is easy to precipitate, the contact diameter is 111
When the number of contacts is about m, there is a problem in that the contact resistance becomes extremely high, 97 contacts in number.
従って１本発明は以上述べた問題を解消し、Ｐ＋型拡散
領域上コンタクトにてコンタクト抵抗の低いバリアメタ
ル構造を有するＣＭＯ８半導体装置の製造方法を提供す
ることを目的とする。Therefore, an object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a CMO8 semiconductor device having a barrier metal structure with a low contact resistance in a contact on a P+ type diffusion region.
本発明はバリアメタル構造を用いた０ＭＯ８半導体装置
の製造方法であって、半導体基板上に形成された中間絶
縁膜にてＮ＋ｍ及びＰ＋型拡散領域に対応する個所を含
む複数の個所にコンタクトホールを開孔し九後、酸化処
理を施し、しかる後にＮ”！拡散領域とＰ＋型拡散領域
とに形成された酸化膜の膜厚差を利用してｐ＋ａｍ散領
域にのみセルファラインでＰ型不純物をイオン注入し、
その表面部にＰ 型拡散領域を形成するようにしたもの
である。The present invention is a method for manufacturing an 0MO8 semiconductor device using a barrier metal structure, in which contact holes are formed at a plurality of locations including locations corresponding to N+m and P+ type diffusion regions in an intermediate insulating film formed on a semiconductor substrate. After nine holes have been opened, oxidation treatment is performed, and then P-type impurities are added to only the p+am diffusion region using a self-line, using the difference in the thickness of the oxide film formed between the N''! diffusion region and the P+ type diffusion region. ion implantation,
A P type diffusion region is formed in the surface portion.
本発明は以上のように、Ｐ型拡散領域の表面部にのみセ
ルファラインで不純物濃度の高いＰ 型拡散領域を形成
するようにしている。この為、コンタクトホールを通し
てバリアメタル構造の配線層全形成する場合、ＰＷ拡散
領域とのコンタクト部ではキャリアが通シ易くなるので
、コンタクト抵抗を低減できる。また弐面部での高不純
物濃度効果から、Ａ！スパイク等を抑制できる。As described above, in the present invention, a P type diffusion region with a high impurity concentration is formed by self-line only on the surface portion of the P type diffusion region. Therefore, when the entire wiring layer of the barrier metal structure is formed through the contact hole, carriers can easily pass through the contact portion with the PW diffusion region, so that the contact resistance can be reduced. Also, due to the high impurity concentration effect on the second side, A! Spikes, etc. can be suppressed.
以下、第１図に基き本発明の一実施例を詳細に説明する
。なお、第２図との同一または相当個所には詞−符号ま
たは相当符号を付し、その説明を省略する。Hereinafter, one embodiment of the present invention will be described in detail based on FIG. Incidentally, the same or equivalent parts as in FIG. 2 are given numerals or equivalent numerals, and their explanations are omitted.
まずｗｃ１図（ａ）は、Ｎ型シリコン基板から成る半導
体基板１１に素子分離を行った後、ゲート絶縁膜１５，
１５ａ、Ｎ型ポリシリコンから成るゲート電極（ポリシ
リコンｆ−）電極）１６，１６ａ。First, in Figure 1 (a) of wc1, after element isolation is performed on a semiconductor substrate 11 made of an N-type silicon substrate, a gate insulating film 15,
15a, gate electrode (polysilicon f-) electrode) 16, 16a made of N-type polysilicon;
！型拡散領域１７．Ｐ＋型拡散領域１８、中間絶縁［２
０を夫々形成し、更にこの中間絶縁膜２０の所定個所に
コンタクトホール２１，２１ａを穿った状態を示してい
る。図中、ｌｌ＆はアクティブ領域、１１ ｂｔｉフィ
ールド領域、１２はＰウェル。! Mold diffusion region 17. P+ type diffusion region 18, intermediate insulation [2
0 is formed, respectively, and contact holes 21 and 21a are further formed at predetermined locations in this intermediate insulating film 20. In the figure, ll& is an active region, 11 is a bti field region, and 12 is a P well.
１３１’ｉＮウエル、また１４はフィールド酸化膜であ
る。131'iN well, and 14 is a field oxide film.
次に＠１１１（ｂ）の如く、酸化処理を施して基板の各
コンタクトホール２１，２１ａ位置に酸化ｇＥ１９゜１
９ａを夫々形成する。ここでＮＭＯ８形成予定領域にお
いては、Ｎ＋型拡散領域１７及びポリシリコンｆｆ−）
電極１６の不純物濃度は２×１０〜５×１０ １ｕｌＫ
と、ＰＭＯ８形成予定領域でのＰ型拡散領域１８の
不純物濃度５×ｌＯ〜ｌＸｌ０ ｍ に比べて高くな
っている。この為、酸化処理を施すとこの不純物濃度差
によシ、？型拡散領域１７及びプリシリコン？−）電極
１６上のコンタクトホール２１位置く形成される酸化膜
１９は３００〜５００Ａ程度、一方ＰＷ拡散領域１８上
のコンタクトホール２７ａ位置に形成される酸化膜１９
ａは１００〜２００Ａ程度となシ膜厚差を有することと
なる。Next, as shown in @111(b), oxidation treatment is performed to oxidize gE19°1 at each contact hole 21, 21a position of the substrate.
9a are formed respectively. Here, in the area where NMO8 is planned to be formed, N+ type diffusion region 17 and polysilicon ff-)
The impurity concentration of the electrode 16 is 2×10 to 5×10 1ulK
This is higher than the impurity concentration of 5×1O to 1X10 m in the P-type diffusion region 18 in the region where the PMO 8 is planned to be formed. For this reason, if oxidation treatment is applied, this difference in impurity concentration will be avoided. Mold diffusion region 17 and pre-silicon? -) The oxide film 19 formed at the contact hole 21 position on the electrode 16 has a thickness of about 300 to 500A, while the oxide film 19 formed at the contact hole 27a position on the PW diffusion region 18
a has a film thickness difference of about 100 to 200A.
なお、ＰＭＯ８形成予定領域のポリシリコンゲート電極
（Ｎ凰）１６ａ上には、ＮＭＯ８形成予定領域の場合と
同様の膜厚の厚い酸化膜１９が形成される。Note that a thick oxide film 19 similar to that in the NMO8 formation region is formed on the polysilicon gate electrode (N-o) 16a in the PMO8 formation region.
しかる後、Ｐ型不純物イオンとしてＢＦ２２７を、例え
ば２０〜４０ ＫｅＶ程度の低加速エネルギーを以って
イオン注入する。この時、酸化膜１９．１９ａの膜厚差
によ、Ｄ、ＮＭＯ８形成予定領域の？型拡散領域１７及
びポリシリコンｆｆ−）電極１６中にはＰ温不純物イオ
ンは注入されず、ＰＭＯ８形成予定領域のＰ型拡散領域
１８のコンタクトホール２１ａ位置にのみイオン注入さ
れ、Ｐ 型不純物層１ｇ＆が形成される。Thereafter, BF227 ions are implanted as P-type impurity ions with a low acceleration energy of, for example, about 20 to 40 KeV. At this time, due to the difference in the thickness of the oxide films 19 and 19a, the area D and NMO8 are planned to be formed. P-type impurity ions are not implanted into the type diffusion region 17 and the polysilicon ff-) electrode 16, but are implanted only at the contact hole 21a position of the P-type diffusion region 18 in the PMO 8 formation area, and the P-type impurity layer 1g& is formed.
次いで第１図（ｅ）に示すように、アニール処理を施し
てイオン注入しｆｃＰ型不純物を活性化させることによ
シ、Ｐ型拡散領域工８の表面近傍にＰ″−１型拡散領域
１８ｂ’に形成する。この後、酸化膜１９゜１９ａを除
去した後、コンタクトホール２１，２１ａを通してバリ
アメタル２２．２２＆及びＡ１層から成る金属層２３，
２３ａとで構成されるバリアメタル構造の配線層２４
； ２２＋２３ 、２４ａ；２２ａ＋２３ａを夫々形成
し、同一基板にＮＭＯ８２５とＰＭＯ８２６とを作シ込
む。Next, as shown in FIG. 1(e), by performing an annealing treatment and ion implantation to activate the fcP type impurity, a P''-1 type diffusion region 18b is formed near the surface of the P type diffusion region 8. After that, after removing the oxide film 19.degree. 19a, the barrier metal 22, 22& and the metal layer 23, which is made of the A1 layer, are formed through the contact holes 21, 21a.
23a and a wiring layer 24 having a barrier metal structure.
22+23, 24a; 22a+23a are formed, respectively, and NMO 825 and PMO 826 are formed on the same substrate.
以上、詳細に説明し九ように１本発明によればＰ＋型拡
散領域の表面部にのみセルファラインでＰ＋＋型拡散領
域を形成するようにしている為１Ｍ スノ々イク等に強
いバリアメタル構造の配線層を形成きるのでＣＭＯ８半
導体装置の高性能化及び高信頼度化を実現することがで
きるという効果がある。As described above in detail, according to the present invention, the P++ type diffusion region is formed only on the surface of the P+ type diffusion region by self-line, so that the barrier metal structure is resistant to 1M snow leakage, etc. Since wiring layers can be formed, there is an effect that higher performance and higher reliability of the CMO8 semiconductor device can be realized.
第１図は本発明の一実施例を説明する工程断面図、＠２
図は従来例を説明する要部断面図である。
１１・・・半導体基板（Ｎ型クリコン基板）、Ｉｌａ・
・・アクティブ領域、１２−・・Ｐウェル、１３・・・
Ｎウェル、１５，１５ａ−・・ゲート絶縁膜、１６１１
６ａ・・・ｒ−ト電極（Ｎ型ポリシリコン）、１７・・
・Ｎ型拡散領域、１８・・・ＰＷ拡散領域、１８ａ・・
・Ｐ 型不純物層、１８ｂ・・・Ｐ 型拡散領域、１９
．１９ａ・・・酸化膜、２０・・・中間絶縁膜、２１，
２１ａ・・・コンタクトホール、２２，２２ａ・・・バ
リアメタル。
２３ 、２３ ＆−・・金属層（ＡＪ）、 ２４ 、２
４ ａ−・・配線層、２５−・ＮＭＯ８，２６・・・Ｐ
ＭＯ８，２７・・・ Ｐ型不純物イオン（ＢＦ２）。Fig. 1 is a process cross-sectional view explaining one embodiment of the present invention, @2
The figure is a sectional view of a main part explaining a conventional example. 11... Semiconductor substrate (N-type crystal substrate), Ila.
...Active region, 12-...P well, 13...
N well, 15, 15a--gate insulating film, 1611
6a...r-to electrode (N-type polysilicon), 17...
・N type diffusion region, 18...PW diffusion region, 18a...
・P type impurity layer, 18b...P type diffusion region, 19
．． 19a... Oxide film, 20... Intermediate insulating film, 21,
21a... Contact hole, 22, 22a... Barrier metal. 23, 23 &--metal layer (AJ), 24, 2
4 a-... wiring layer, 25-...NMO8, 26...P
MO8,27... P-type impurity ion (BF2).
Claims (1)
周辺部にＮ＾＋型拡散領域とＰ＾＋型拡散領域とを有す
る半導体基板上に中間絶縁膜を形成すると共に、少なく
とも上記Ｎ＾＋型拡散領域と上記Ｐ＾＋型拡散領域に対
応する個所にコンタクトホールを開孔する工程と、 （ｂ）基板に酸化処理を施して、少なくとも上記Ｎ＾＋
型拡散領域及び上記Ｐ＾＋型拡散領域上に夫々厚目及び
薄目の酸化膜を形成し、しかる後に上記Ｐ＾＋型拡散領
域にセルフアラインでＰ型不純物をイオン注入する工程
と、 （ｃ）上記イオン注入されたＰ型不純物を活性化して、
上記Ｐ＾＋型拡散領域の表面部にＰ＾＋＾＋型拡散領域
を形成し、この後上記コンタクトホールを通してバリア
メタル構造の配線層を形成する工程とを含むことを特徴
とする半導体装置の製造方法。(1) (a) An intermediate insulating film is formed on a semiconductor substrate having a gate insulating film, a gate electrode, and an N^+ type diffusion region and a P^+ type diffusion region in their peripheral areas, and at least the above N^+ type diffusion region is formed on the semiconductor substrate. (b) performing oxidation treatment on the substrate to form at least the above N^+ type diffusion region;
forming thick and thin oxide films on the P^+ type diffusion region and the P^+ type diffusion region, respectively, and then ion-implanting P type impurities into the P^+ type diffusion region in a self-aligned manner; ) Activating the ion-implanted P-type impurity,
A semiconductor device comprising the steps of: forming a P^+^+ type diffusion region on a surface portion of the P^+ type diffusion region, and then forming a wiring layer having a barrier metal structure through the contact hole. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61178637A JPS6336555A (en) | 1986-07-31 | 1986-07-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61178637A JPS6336555A (en) | 1986-07-31 | 1986-07-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6336555A true JPS6336555A (en) | 1988-02-17 |
Family
ID=16051938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61178637A Pending JPS6336555A (en) | 1986-07-31 | 1986-07-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6336555A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01274454A (en) * | 1988-04-26 | 1989-11-02 | Seiko Epson Corp | Semiconductor and manufacture thereof |
| JPH01312868A (en) * | 1988-06-10 | 1989-12-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH02208961A (en) * | 1989-02-08 | 1990-08-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH1056065A (en) * | 1997-06-02 | 1998-02-24 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| US5904519A (en) * | 1996-06-20 | 1999-05-18 | Nec Corporation | Method of manufacturing Bi-CMOS |
-
1986
- 1986-07-31 JP JP61178637A patent/JPS6336555A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01274454A (en) * | 1988-04-26 | 1989-11-02 | Seiko Epson Corp | Semiconductor and manufacture thereof |
| JPH01312868A (en) * | 1988-06-10 | 1989-12-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH02208961A (en) * | 1989-02-08 | 1990-08-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5904519A (en) * | 1996-06-20 | 1999-05-18 | Nec Corporation | Method of manufacturing Bi-CMOS |
| JPH1056065A (en) * | 1997-06-02 | 1998-02-24 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR940009360B1 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0426542B2 (en) | ||
| JPH0653168A (en) | Manufacture of titanium silicide contact | |
| JPH08213479A (en) | Manufacture of mis transistor and semiconductor device | |
| JPS6245708B2 (en) | ||
| JPS6336555A (en) | Manufacture of semiconductor device | |
| JPS63305546A (en) | Manufacture of semiconductor integrated circuit device | |
| JPS61182267A (en) | Manufacture of semiconductor device | |
| EP0712152B1 (en) | Method of manufacturing a semiconductor device | |
| JP2550691B2 (en) | Method for manufacturing semiconductor device | |
| JPH06295983A (en) | Semiconductor device and its manufacture | |
| JPS621276A (en) | Mos type semiconductor device | |
| JPH07161826A (en) | Manufacture of semiconductor device | |
| JPH0685178A (en) | Semiconductor integrated circuit device | |
| JPS61287160A (en) | Manufacture of mos type semiconductor device | |
| JP2720509B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JPH06132523A (en) | Manufacture of mos transistor | |
| JP2720592B2 (en) | Method for manufacturing semiconductor device | |
| JP2828644B2 (en) | Method for manufacturing semiconductor integrated circuit | |
| JPS60134469A (en) | Manufacture of semiconductor device | |
| JPH04363019A (en) | Manufacture of semiconductor device | |
| JPH0379080A (en) | High breakdown strength mos transistor | |
| JPH0897292A (en) | Production of mos transistor and complementary mos transistor | |
| JPH08288399A (en) | Manufacture of cmos semiconductor device | |
| JPS62181459A (en) | Manufacture of semiconductor device |