JPH0379080A - High breakdown strength mos transistor - Google Patents

Abstract

PURPOSE:To enhance breakdown strength by forming a LOCOS oxide film simultaneously with an element isolating LOCOS oxide film between a channel region and a drain region, and forming an offset layer between the channel region and the drain region. CONSTITUTION:LOCOS oxide film 3, 13 are formed between a channel region and a drain region by thermal oxidation, an Si3N4 film and an SiO2 film on the surface are removed by etching, a gate oxide film 4 is formed, polysilicon is laminated thereon, patterned, and a polysilicon gate electrode 5 is formed. Then, a source layer 6 and a drain layer 7 are formed, P-type impurity ions are implanted with the electrode 5 and the film 13 as masks, and an offset layer 18 is formed on a region with the ion implanted P-type impurity before the film 13 is formed. Thus, high breakdown strength of 100V or higher can be realized without particularly increasing the thickness of the gate oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high voltage MO8) transistor having a structure in which electric field concentration is alleviated by an offset layer.

[Conventional technology]

In order to increase the breakdown voltage of a MOS transistor, it is important to alleviate the electric field concentration on the gate oxide film on the drain side.

FIG. 3 shows the structure of an example of a conventional high-voltage MO8) transistor of this type.

In the figure, 1 is an N-type substrate, 2 is an N+ channel horn, 3 is a LOCOS oxide film, 4 is a gate oxide film, 5 is a polysilicon f-) electrode, 6 is a P+ source layer, 7 is a P+ drain layer, 8 is a P offset layer, 9 is a CVD silicon oxide film, 10 is an At source electrode, and 111/'bt drain electrode.

The figure shows an example of a P-channel MO8) transistor.

Conventional high voltage MO8)? The transistor is separated from other elements by a LOCOS oxide film 3, and a P offset layer 8 with a spacing of several microns is provided between the channel layer under the polysilicon dirt electrode 5 and the P+ drain layer by ion implantation, and the drain side Structures have been adopted to alleviate the electric field concentration in the dirt oxide film 4.

The figure shows an example in which the offset layer is provided only on the drain side, but due to the symmetry between the source layer 6 and the drain layer 7, the offset layer may also be provided on the source side.

[Problem to be solved by the invention]

In the conventional MOS (MOS) transistor with the above structure,
It is difficult to achieve a high breakdown voltage of 100 V or more, and to achieve this, it was necessary to take measures such as increasing the thickness of the dirt oxide film.

In actual LSIs, high voltage resistance is required for the output MOS transistor, and high speed is required for the internal LOGIC MOS transistor, but it is said that the thickness of the dirt oxide film can be changed in the output MO8) Rungis 2850G CMOS transistor. Cumbersome measures have been taken.

The present invention has been made in view of the above-mentioned circumstances, and eliminates the need to make the gate oxide film particularly thick (for example, for internal LOGI
400X to 500X equivalent to CMOS transistor
The purpose of the present invention is to provide a Mos transistor with a high voltage resistance of 100V or more.

[Means to solve the problem]

forming a LOCOSIII film simultaneously with the element isolation LOCOS oxide film between the channel region and the drain region in the high breakdown voltage MO8) transistor of the present invention, and implanting ions into the region before forming the LOCOS oxide film; An offset layer is formed between the channel region and the drain region by implanting ions using an oxide film and a polysilicon gate electrode as a mask.

〔Example〕

FIG. 1 shows an embodiment of the invention.

In the figure, 1, 2 t 3, 4, 5, 6,
7, 910.11 indicate the same or corresponding parts as the same reference numerals in FIG. 3, 13 indicates the LOCOS oxide film formed between the channel region and the drain region, and 18 indicates the LOCOS
This is an offset layer that bypasses the oxide film 13.

Due to the presence of the LOCOS oxide film 13, the voltage resistance between the drain and the dirt is improved compared to the conventional structure.
A product with a high breakdown voltage of V or more can be obtained.

Hereinafter, a method for manufacturing a MOS transistor having the above structure will be briefly explained with reference to FIG.

In the example of a P-channel type, a 5i02 film is placed on the surface of the N-type substrate 1,
A Si3N4 film is formed on the 5i02 film, and a Si3N4 film is formed on the 5i5N4 film.
The part of the LOCOS oxide film region formed between the device isolation LOGoS oxide film region of the film, the channel region and the drain region is removed by etching, and the ion implantation is performed to form a channel strike and the 5K3 between the channel region and the drain region.
Perform Nb injection [Figure (, )).

Next, LOCOSil films 3 and 13 are formed by thermal oxidation, the Si3N4 film and the 5IO2 film on the surface are etched away [Figure (b)), a dirt oxide film 4 is formed, and polysilicon is laminated thereon. Then, patterning is performed to form a polysilicon gate electrode 5 [Figure (C)].

Subsequently, a source layer 6 and a drain layer 7 are formed by ion implantation [Figure (d)), and a polysilicon gate electrode 5 and L
P-type impurity ions are implanted using the OCOS oxide film 13 as a mask, and the offset layer 18 is formed with the P-type impurity ions implanted into the region before forming the LOCOS oxide film 13 [Figure (e)]. From then on, in the conventional case Similarly, the 5i02 film 9 of the intermediate insulating layer
is deposited, a contact portion is opened, and PT is vapor-deposited on the surface, followed by f-turning to form an At source electrode 10 and an At drain electrode 11 [Figure (f)].

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to achieve a high withstand voltage of 100 V or more without making the dirt oxide film particularly thick. This has the effect of eliminating the need to take the troublesome step of making it thicker than normal.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing one embodiment of the present invention, and Fig. 2 is a schematic diagram showing an embodiment of the present invention.
A schematic diagram showing the manufacturing method of a MOS transistor with the structure shown in the figure, Figure 3 is a conventional high-voltage MO8) of this type.
FIG. 2 is a schematic diagram showing the structure of an example of a nonstar. 1...N-type substrate, 2...N+ channel stock
3゜13...LOCOS oxide film, 4...Dart oxide film, 5...Polysilicon gate electrode, 6...P+ source layer, 7...P+ drain no, 9...CVD silicon oxide [, 10...At-source electrode, 11...
- At drain electrode, 18...P offset layer, Note that the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] It is isolated from other elements by a LOCOS oxide film, the gate electrode is formed of polysilicon, and the LO
A COS oxide film is formed, and an offset layer is formed between the channel region and the drain region by ion implantation into the region before forming the LOCOS oxide film and ion implantation using the LOCOS oxide film and the polysilicon gate electrode as masks. A high voltage MOS transistor characterized by: