JPH06120497A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance a withstand voltage by forming an electric field alleviating region by dividing it into low and high concentration regions in a MOS transistor. CONSTITUTION:An element isolation region 12 is formed on an upper layer of an N-type semiconductor substrate 11, a first electric field alleviating region 13 is formed at one side under the region 12, a second electric field alleviating region 31 having lower concentration than that of the region 13 is connected to the region 13 to be formed at the other side. A gate electrode 15 to be overlapped on the region 12 is formed on the substrate 11 of the side of a second electric field alleviating region 31 through a gate insulating film 14. A P<+> type source region 16 is formed on the upper layer of the substrate 11 opposite to the region 12 side to the electrode 15, and a P<+> type drain region 17 is formed on the upper layer of the substrate 11 of the region 12 side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MOS transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional high breakdown voltage MOS transistor will be described with reference to the schematic sectional view of FIG. In the figure, an LOD (LOCOS Offset Drain) type P-channel MOS transistor 5 is shown as an example.

As shown in the figure, an element isolation region 12 is formed in the upper layer of the N type semiconductor substrate 11. A P ⁻ electric field relaxation region 51 is formed on the N-type semiconductor substrate 11 below the element isolation region 12. A gate insulating film 14 is formed on the N-type semiconductor substrate 11 on one side of the element isolation region 12. A gate electrode 15 is formed on the gate insulating film 14 on the element isolation region 12 side so as to overlap the element isolation region 12.

P ⁺ is formed on the upper layer of the N-type semiconductor substrate 11 opposite to the element isolation region 12 side with respect to the gate electrode 15.
The source region 16 is formed. In addition, the element isolation region 1
In the upper layer of the N-type semiconductor substrate 11 opposite to the gate electrode 15 side with respect to 2, the P ⁻ connected to the P ⁻ electric field relaxation region 51 is formed.
^{+ A} drain region 17 is formed.

Further, an interlayer insulating film 18 is formed so as to cover the gate electrode 15, and is formed on the P ⁺ source region 16 and P
Contact holes 19 and 20 are formed in the interlayer insulating film 18 on the ⁺ drain region 17. A source electrode 21 and a drain electrode 22 connected to the P ⁺ source region 16 and the P ⁺ drain region 17 are formed in each of the contact holes 19 and 20.

[0006]

However, in the MOS transistor having the above structure, the P ^- channel stop region under the element isolation region is used as the electric field relaxation region for high breakdown voltage. Therefore, the degree of freedom regarding the concentration is small. Therefore, if the channel stop performance is prioritized, the breakdown voltage cannot be sufficiently obtained. On the other hand, if an attempt is made to secure sufficient breakdown voltage, the channel stop performance will be insufficient.

In particular, in order to realize high integration of the element, it is necessary to reduce the thickness of the element isolation region or reduce its width. Therefore, it is necessary to increase the concentration of the P ⁻ electric field relaxation region that acts as the channel stop region. In the high breakdown voltage transistor, when the P ⁻ electric field relaxation region as the channel stop region has a high concentration, the depletion layer becomes difficult to expand. Therefore, avalanche breakdown is likely to occur, and high breakdown voltage cannot be secured.

An object of the present invention is to provide a MOS transistor excellent in high breakdown voltage and a method for manufacturing the same.

[0009]

SUMMARY OF THE INVENTION The present invention is a MOS transistor and a method for manufacturing the same made to achieve the above object. The first MOS transistor has the following configuration. That is, the element isolation region is formed in the upper layer of the semiconductor substrate. A first electric field relaxation region is formed on one side of the semiconductor substrate below the element isolation region, and a second electric field relaxation of the same conductivity type as the first electric field relaxation region and a low concentration is formed on the other side. A region is formed so as to be connected to the first electric field relaxation region. Further, a gate insulating film is formed on an upper layer of the semiconductor substrate on the side of the second electric field relaxation region, and a gate electrode is formed on the upper surface of the semiconductor substrate so as to overlap the element isolation region on the second electric field relaxation region. ing. A source region is formed in the upper layer of the semiconductor substrate opposite to the element isolation region side with respect to the gate electrode. Further, a drain region connected to the first electric field relaxation region is formed on the upper layer of the semiconductor substrate opposite to the gate electrode side with respect to the element isolation region.

As a method of manufacturing the first MOS transistor, in the first step, an element isolation region is provided in the upper layer of the semiconductor substrate, and the first electric field relaxation region is provided on one side of the semiconductor substrate below the element isolation region. And a second electric field relaxation region having the same conductivity type as that of the first electric field relaxation region and having a low concentration is connected to the first electric field relaxation region on the other side. Next, in a second step, after forming a gate insulating film on the upper layer of the semiconductor substrate on the second electric field relaxation region side, the gate electrode is gate-insulated so as to overlap the element isolation region on the second electric field relaxation region. Form on the film. Then, in a third step, a source region is formed in an upper layer of the semiconductor substrate opposite to the element isolation region side with respect to the gate electrode, and a source region is formed in an upper layer of the semiconductor substrate opposite to the gate electrode side with respect to the element isolation region. A drain region connected to the first electric field relaxation region is formed.

As the second MOS transistor, in the first MOS transistor, the first electric field relaxation region is formed on the semiconductor substrate below the element isolation region. The gate electrode is formed on the gate insulating film without overlapping the element isolation region. The second electric field relaxation region is formed in the upper layer of the semiconductor substrate between the gate electrode and the first electric field relaxation region.

As the second MOS transistor manufacturing method, in the first step, the element isolation region is formed in the upper layer of the semiconductor substrate, and the first electric field relaxation region is formed in the semiconductor substrate below the element isolation region. Form. Next, in a second step, a gate insulating film is formed on the upper surface of the semiconductor substrate on one side of the element isolation region, and a gate electrode is formed on the upper surface. Then, in a third step, a second electric field relaxation region of the same conductivity type as the first electric field relaxation region and having a low concentration is formed in an upper layer of the semiconductor substrate between the element isolation region and the gate electrode.
In the fourth step, a source region is formed in an upper layer of the semiconductor substrate opposite to the second electric field relaxation region side with respect to the gate electrode, after being formed by connecting to the electric field relaxation region of
A drain region connected to the first electric field relaxation region is formed in an upper layer of the semiconductor substrate opposite to the gate electrode side with respect to the element isolation region.

[0013]

In the first and second MOS transistors, the first electric field relaxation region is provided on the upper layer of the semiconductor substrate on the gate electrode side with respect to the first electric field relaxation region and has the same conductivity type as the first electric field relaxation region. By forming the second electric field relaxation region having a concentration lower than that of the relaxation region, the concentration of the first electric field relaxation region is set to a concentration at which the channel stop performance is sufficiently secured. At the same time, the concentration of the second electric field relaxation region is set to a concentration that ensures a high withstand voltage.

In the first and second manufacturing methods, the second method is used.
Since the concentration of the electric field relaxation region is lower than that of the source region or the drain region by one or two orders of magnitude, impurities for forming the second electric field relaxation region are formed on the entire surface of the semiconductor substrate without using, for example, an ion implantation mask. It becomes possible to introduce.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. In the figure, as an example, LOD (LOC
OS Offset Drain) P-channel MO
The S-transistor 1 is shown. As shown in the figure, an element isolation region 12 is formed in the upper layer of, for example, an N-type semiconductor substrate 11. A first electric field relaxation region 13 is formed on one side of the N-type semiconductor substrate 11 below the element isolation region 12. On the other side, the first electric field relaxation region 1
A second electric field relaxation region 31 having the same conductivity type (P type) as that of No. 3 and a low concentration is formed so as to be connected to the first electric field relaxation region 13.

A gate insulating film 14 is formed on the upper surface of the N-type semiconductor substrate 11 on the second electric field relaxation region 31 side with respect to the element isolation region 12. A gate electrode 15 is formed on the gate insulating film 14 on the second electric field relaxation region 31 side so as to overlap the element isolation region 12 on the second electric field relaxation region 31. As shown in the figure, the normal gate insulating film 14 is also formed on the other surface of the N-type semiconductor substrate 11. The gate electrode 1
5, a P ⁺ source region 16 is formed in the upper layer of the N-type semiconductor substrate 11 opposite to the element isolation region 12 side. Further, a P ⁺ drain region 17 connected to the first electric field relaxation 13 is formed in the upper layer of the N-type semiconductor substrate 11 opposite to the gate electrode 15 side with respect to the element isolation region 12.

Further, an interlayer insulating film 18 is formed so as to cover the entire surface of the gate electrode 15 side. Further, the contact hole 19 is formed in the interlayer insulating film 18 and the gate insulating film 14 on the P ⁺ source region 16 and the P ⁺ drain region 17, respectively.
20 are formed. Each contact hole 19, 20
A source electrode 21 and a drain electrode 22 that are connected to the P ⁺ source region 16 and the P ⁺ drain region 17 are formed in the. The P-channel MOS transistor 1 is configured as described above.

In the P-channel MOS transistor 1, the second electric field relaxation region 3 is formed in the upper layer of the N-type semiconductor substrate 11 on the gate electrode 15 side with respect to the first electric field relaxation region 13.
By forming 1, the concentration of the first electric field relaxation region 13 is set to a concentration at which the channel stop performance is sufficiently ensured. The concentration of the second electric field relaxation region 31 is set to a concentration that ensures a high breakdown voltage.

Next, the manufacturing method of the first embodiment will be described with reference to the manufacturing process chart of FIG. As shown in (1) of FIG. 2, in the first step, an oxidation mask 41 for forming a LOCOS oxide film to be an element isolation region is formed on the semiconductor substrate 11 by a normal LOCOS method. The oxidation mask 41 is usually formed with a laminated structure of a silicon oxide (SiO ₂ ) film and a silicon nitride (SiN) film.

Then, for example, boron difluoride (BF ₂ ) is ion-implanted as a P-type impurity into the upper layer of the N-type semiconductor substrate 11 by a normal ion implantation method using the oxidation mask 41 as an ion implantation mask. To do. The ion implantation condition at this time is that the dose amount is 1 × 10 ¹² / cm ² to
It is set to about 5 × 10 ¹² / cm ² .

Subsequently, as shown in FIG. 2B, an ion implantation mask 42 is formed by photolithography technique so as to cover approximately half of the portion where the element isolation region 12 is formed. Then, by a normal ion implantation method, a first electric field relaxation region (1) described later is formed on the upper layer of the N-type semiconductor substrate 11.
For example, boron difluoride (BF ₂ ) is ion-implanted as a P-type impurity for forming 3). The dose amount of this ion implantation is set to a value larger than the dose amount of the ion implantation described in (1) of the above figure. Next, the ion implantation mask 42 is removed by, for example, an asher process.

Thereafter, as shown in (3) of FIG.
The element isolation region 12 is formed in the upper layer of the N-type semiconductor substrate 11 by performing OS oxidation, and the element isolation region 1 is also formed.
A first electric field relaxation region 13 and a second electric field relaxation region 31 connected to the first electric field relaxation region 13 are formed on the N-type semiconductor substrate 11 on the lower side of 2. Next, the oxidation mask 41 is removed by etching, for example.

Then, the second step shown in FIG. 2 (4) is performed. In this step, for example, by chemical vapor deposition,
The gate insulating film 14 is formed on the N-type semiconductor substrate 11. After that, a gate electrode forming film (43) is formed by a chemical vapor deposition method, and then the second electric field relaxation region 3 is formed by an ordinary photolithography technique and etching.
The second electric field relaxation region 31 on the gate insulating film 14 is made to overlap with the element isolation region 12 on the first insulating film 14.
On the side, the gate electrode 15 is formed by the gate electrode forming film (43).

Subsequently, a third step shown in FIG. 2 (5) is performed. In this step, for example, boron difluoride (BF ₂ ) is ion-implanted as a P-type impurity by a normal ion-implantation method. Then, P is formed on the upper layer of the N-type semiconductor substrate 11 opposite to the element isolation region 12 side with respect to the gate electrode 15.
⁺ Source region 16 is formed. At the same time, a P ⁺ drain region 17 is formed on the upper layer of the N-type semiconductor substrate 11 opposite to the gate electrode 15 side with respect to the element isolation region 12 in a state of being connected to the first electric field relaxation region 13. As the ion implantation conditions, the dose amount is, for example, 1 × 10 ¹⁵ / cm 2.
^It is set to about ^{2 to} 5 × 10 ¹⁵ / cm ² .

Thereafter, as shown in FIG. 2 (6), an interlayer insulating film 18 is formed by chemical vapor deposition so as to cover the entire surface on the gate electrode 15 side. Then, the P ⁺ source region 16 is formed by photolithography and etching.
Contact holes 19 and 20 are formed in the interlayer insulating film 18 and the gate insulating film 14 above and on the P ⁺ drain region 17. Then, a source electrode 21 and a drain electrode 22 connected to the P ⁺ source region 16 and the P ⁺ drain region 17 are formed in each of the contact holes 19 and 20 by a normal wiring forming technique. P-channel MOS transistor 1 is formed as described above.

In the manufacturing method of the first embodiment, since the concentration of the second electric field relaxation region 31 is lower than that of the first electric field relaxation region 13, the ion implantation mask is not used and the N type semiconductor substrate is not used. It becomes possible to introduce impurities forming the second electric field relaxation region 31 into the entire surface of 11. Therefore,
There is no need to perform the step of forming the ion implantation mask for forming the second electric field relaxation region 31.

This manufacturing method can also be applied to CMOS. In this case, for example, in order to form a channel stop region of CMOS, ion implantation is performed without forming an ion implantation mask for forming the second electric field relaxation region 31. To form the P ⁻ channel stop region, the dose amount is set to a value added to the dose amount in the above ion implantation. Further, in order to form the N ⁻ channel stop region, the dose amount is set to a value subtracted from the dose amount in the ion implantation. Therefore, N-type impurities (for example, phosphorus) may be implanted with a dose amount matching the set value.

Next, a second embodiment will be described with reference to the schematic cross-sectional view of FIG. In the figure, as an example, LOD (LOCO
S Offset Drain) type P-channel MOS
Transistor 2 is shown. Further, the same components as those of the P-channel MOS transistor 1 described with reference to FIG. As shown in the figure, an element isolation region 12 is formed in the upper layer of the N-type semiconductor substrate 11. A first electric field relaxation region 13 is formed on the N-type semiconductor substrate 11 below the element isolation region 12.

N on one side of the element isolation region 12
A gate insulating film 14 is formed on the upper surface of the semiconductor substrate 11 of the mold. The gate electrode 1 is formed on the gate insulating film 14.
5 is formed. As shown in the figure, the normal gate insulating film 14 is also formed on the other surface of the N-type semiconductor substrate 11. In addition, in the upper layer of the N-type semiconductor substrate 11 between the element isolation region 12 and the gate electrode 15, the same conductivity type (P-type) as the first electric field relaxation region 13 is formed.
The low-concentration second electric field relaxation region 32 is formed so as to be connected to the first electric field relaxation region 13.

A P ⁺ source region 16 is formed in the upper layer of the N-type semiconductor substrate 11 opposite to the second electric field relaxation region 32 side with respect to the gate electrode 15. A P ⁺ drain region 17 is formed on the upper layer of the N-type semiconductor substrate 11 on the side opposite to the gate electrode 15 side with respect to the element isolation region 12 so as to be connected to the first electric field relaxation region 13.

Further, an interlayer insulating film 18 is formed so as to cover the entire surface on the gate electrode 15 side. Further, the contact hole 19 is formed in the interlayer insulating film 18 and the gate insulating film 14 on the P ⁺ source region 16 and the P ⁺ drain region 17, respectively.
20 are formed. Each contact hole 19, 20
A source electrode 21 and a drain electrode 22 that are connected to the P ⁺ source region 16 and the P ⁺ drain region 17 are formed in the. The P-channel MOS transistor 2 is configured as described above.

In the P-channel MOS transistor 2, since the first electric field relaxation region 13 and the second electric field relaxation region are formed, the concentration of the first electric field relaxation region 13 sufficiently secures the channel stop performance. The concentration of the second electric field relaxation region 31 is set to a concentration that ensures a high withstand voltage.

Although not shown, so-called LDDMO
In the case where the P-channel MOS transistor 2 is formed on the same substrate as the S-transistor, when the LDD region is formed, the L-region is formed in the second electric field relaxation region 32.
It is also possible to form the P-channel MOS transistor 2 by forming a mask so that the DD ion implantation is not performed.

Next, the manufacturing method of the second embodiment will be described with reference to the manufacturing process chart of FIG. As shown in FIG. 4A, in the first step, the oxidation mask 41 is formed on the upper surface of the N-type semiconductor substrate 11 in the same manner as described in FIG. ₂ ) Film and silicon nitride (S
iN) film and a laminated structure. Then, for example, boron difluoride (BF ₂ ) is ion-implanted into the upper layer of the N-type semiconductor substrate 11 as a P-type impurity by a normal ion implantation method using the oxidation mask 41 as an ion implantation mask. Then, LOCOS oxidation is performed to form the element isolation region 12 on the upper layer of the N-type semiconductor substrate 11, and the N-type semiconductor substrate 1 below the element isolation region 12 is formed.
First, the first electric field relaxation region 13 is formed. The first electric field relaxation region 13 can be formed simultaneously with the P ⁻ channel stop region of another MOS transistor.

Next, the oxidation mask 41 is removed by etching, for example. Then, the second step shown in FIG. 4B is performed. In this step, the gate insulating film 14 is formed on the upper surface of the N-type semiconductor substrate 11 in the same manner as described in (4) of FIG. Further, the element isolation region 12
A gate electrode 15 is formed on the upper surface of the gate insulating film 14 on one side.

Subsequently, the third step shown in FIG. 4C is performed. In this step, as a P-type impurity, for example, boron difluoride (BF) is formed on the upper layer of the N-type semiconductor substrate 11 by a normal ion implantation method using the gate electrode 15 and the element isolation region 12 as an ion implantation mask. ₂ ) is ion-implanted. A second electric field relaxation region 32 of the same conductivity type as the first electric field relaxation region 13 and having a low concentration is formed on the upper layer of the N-type semiconductor substrate 11 between the element isolation region 12 and the gate electrode 15. It is formed so as to be connected to the electric field relaxation region 13. As the ion implantation conditions, the dose amount is set to, for example, about 1 × 10 ¹² / cm ^{2 to} 5 × 10 ¹² / cm ² . In this ion implantation, the N-type semiconductor substrate 11
Although boron was ion-implanted into the entire upper layer, there is no effect because the dose amount in the subsequent ion implantation step is larger than the dose amount by one digit or more.

Then, a fourth step shown in FIG. 4D is performed. In this step, the ion implantation mask 4 that covers the second electric field relaxation region 32 formed between the gate electrode 15 and the element isolation region 12 is formed by a normal photolithography technique.
4 is formed. After that, by a normal ion implantation method, P
As a type impurity, for example, boron difluoride (BF ₂ ) is ion-implanted into the upper layer of the N-type semiconductor substrate 11. Then, the P ⁺ source region 1 is formed in the upper layer of the N-type semiconductor substrate 11 opposite to the second electric field relaxation region 32 side with respect to the gate electrode 15.
6 is formed. At the same time, a P ⁺ drain region 17 is provided on the upper layer of the N-type semiconductor substrate 11 opposite to the gate electrode 15 side with respect to the element isolation region 12, and the first electric field relaxation region 13
It is formed in a state of being connected to. The ion implantation conditions are, for example, a dose of 1 × 10 ¹⁵ / cm ^{2 to} 5 × 10 ^15.
Set to about / cm ² .

Then, the ion implantation mask 44 is removed by, for example, an asher process. Thereafter, as shown in (5) of Figure 4, in the same manner as described in the Figure 2 (6), an interlayer insulating film 18 to cover the entire surface of the gate electrode 15 side, then P ⁺ source On area 16 and P ⁺
Contact holes 19 and 20 are formed in the interlayer insulating film 18 and the gate insulating film 14 on the drain region 17.
Then, a source electrode 21 and a drain electrode 22 connected to the P ⁺ source region 16 and the P ⁺ drain region 17 are formed in each contact hole 19, 20. P-channel MOS transistor 2 is formed as described above.

In the manufacturing method of the second embodiment, the concentration of the second electric field relaxation region 32 is set to the P ⁺ source regions 16 and P ^+.
Since it is lower than that of the drain region 17 by two orders of magnitude, it is possible to introduce the impurities forming the second electric field relaxation region 32 into the entire surface of the N-type semiconductor substrate 11 without using an ion implantation mask. Therefore, it is not necessary to perform the step of forming the ion implantation mask for forming the second electric field relaxation region 32.

In the first and second embodiments, the P channel M
The OS transistor has been described, but the N-channel MO
The same applies to the S transistor. In this case,
The polarities of the components are reversed. The ion implantation conditions described in the first and second embodiments are examples, and the numerical values are not limited.

[0041]

As described above, according to the MOS transistor of the present invention, the same conductivity type as that of the first electric field relaxation region is provided in the upper layer of the semiconductor substrate on the gate electrode side with respect to the first electric field relaxation region. In addition, since the second electric field relaxation region having a lower concentration than that of the first electric field relaxation region is formed, the first electric field relaxation region can be formed at a concentration at which the channel stop performance is sufficiently secured. At the same time, the electric field relaxation region can be formed at a concentration that ensures a high withstand voltage. Therefore MOS
The transistor has high breakdown voltage without being affected by avalanche breakdown.

Further, according to the above manufacturing method, since the concentration of the electric field relaxation region is lower than that of the source region or the drain region by two orders of magnitude, the electric field relaxation region is formed on the entire surface of the semiconductor substrate without using an ion implantation mask, for example. It becomes possible to introduce impurities to be formed. Therefore, the electric field relaxation region can be formed without increasing the number of steps using a mask, and the burden on the manufacturing process is minimized.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a manufacturing process diagram of the first embodiment.

FIG. 3 is a schematic configuration sectional view of a second embodiment.

FIG. 4 is a manufacturing process diagram of the second embodiment.

FIG. 5 is a schematic configuration sectional view of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-channel MOS transistor 2 P-channel MOS transistor 11 N-type semiconductor substrate 12 Element isolation region 13 First electric field relaxation region 14 Gate insulating film 15 Gate electrode 16 P ⁺ source region 17 P ⁺ drain region 31 Second electric field relaxation Region 32 Second electric field relaxation region

Claims (4)

[Claims] 1. An element isolation region formed in an upper layer of a semiconductor substrate, a first electric field relaxation region formed on one side of the semiconductor substrate below the element isolation region, and the same conductivity as the first electric field relaxation region. A second type electric field relaxation region formed in a state of being connected to the first electric field relaxation region on the other side of the semiconductor substrate below the device isolation region, A gate insulating film formed on the upper layer of the semiconductor substrate at least on the other side of the region, on the gate insulating film on the second electric field relaxation region side, and on the second side.
A gate electrode formed on the element isolation region on the electric field relaxation region of, a source region formed on an upper layer of the semiconductor substrate opposite to the gate electrode on the element isolation region side, and for the element isolation region And a drain region formed in an upper layer of the semiconductor substrate opposite to the gate electrode side so as to be connected to the first electric field relaxation region. 2. An element isolation region is formed in an upper layer of the semiconductor substrate, a first electric field relaxation region is formed on one side of the semiconductor substrate below the element isolation region, and the first electric field relaxation region is formed on the other side of the semiconductor substrate. A first step of forming a second electric field relaxation region of the same conductivity type as the first electric field relaxation region and having a low concentration in a state of being connected to the first electric field relaxation region; After forming a gate insulating film in the upper layer of the semiconductor substrate on the side of the second electric field relaxation region, on the gate insulating film on the side of the second electric field relaxation region and on the element isolation region on the second electric field relaxation region. A second step of forming a gate electrode on the gate electrode, and forming a source region on the upper layer of the semiconductor substrate opposite to the element isolation region side with respect to the gate electrode, Is the opposite semiconductor Method for manufacturing a MOS transistor and performing a third step of forming a drain region connected to the upper plate in the first field limiting region. 3. An element isolation region formed in an upper layer of the semiconductor substrate, a first electric field relaxation region formed in the semiconductor substrate below the element isolation region, and an upper surface of the semiconductor substrate on one side of the element isolation region. A gate electrode formed via a gate insulating film, and a region of the same conductivity type as that of the first electric field relaxation region and having a low concentration, between the element isolation region and the gate electrode. A second electric field relaxation region formed in a state of being connected to the first electric field relaxation region in an upper layer, and formed in an upper layer of the semiconductor substrate opposite to the second electric field relaxation region side with respect to the gate electrode. A source region and a drain region formed in an upper layer of the semiconductor substrate opposite to the gate electrode side with respect to the element isolation region, the drain region being connected to the first electric field relaxation region. MOS transistor to be butterflies. 4. A first step of forming an element isolation region in an upper layer of a semiconductor substrate and forming a first electric field relaxation region in the semiconductor substrate below the element isolation region, and one side of the element isolation region. A second step of forming a gate insulating film on the upper surface of the semiconductor substrate and further forming a gate electrode on the upper surface of the gate insulating film, and an upper layer of the semiconductor substrate between the element isolation region and the gate electrode. And a third step of forming a second electric field relaxation region of the same conductivity type as the first electric field relaxation region and having a low concentration in a state of being connected to the first electric field relaxation region, and to the gate electrode. A source region is formed in an upper layer of the semiconductor substrate opposite to the second electric field relaxation region side, and the first region is formed in an upper layer of the semiconductor substrate opposite to the gate electrode side with respect to the element isolation region. And a fourth step of forming a drain region connected to the first electric field relaxation region.