JPH01309496A - Control unit selecting circuit - Google Patents

Abstract

PURPOSE:To attain the operation control and state confirmation of each control unit by means of a common operation display device and to make the entire device inexpensive by adopting the constitution such that a digital signal path and an analog signal path from plural control units are selected and switched with a time difference and the path is connected to the common operation display device. CONSTITUTION:The digital signal path between the selected control unit and the common operation display device is connected by using a 1st selection control signal outputted from a 1st delay circuit 3-1 receiving a selection signal outputted from a selector 1-1. Moreover, the analog signal path between the selected control unit and the common operation display device is connected by using a 2nd selection control signal being an AND signal between a signal outputted from a 2nd delay circuit 4-1 receiving the 1st selection control signal and a selection signal outputted from the selector 1-1. In the case of disconnecting the connection path, the analog signal path from the control unit selected is disconnected immediately by using a non-selection signal outputted from the selector 1-1 and the digital signal path from the control unit selected is disconnected by using the non-selection signal retarded from the non- selection signal via the 1st delay circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a control unit selection circuit that selects one of a plurality of control units and connects it to an operation display, and in particular, a control unit selection circuit that selects one of a plurality of control units and connects it to an operation display. This invention relates to a control unit selection circuit that selectively opens and closes signal paths.

[Prior Art] FIG. 5 is a block diagram of a conventional control unit selection circuit, in which (1) is a selection switch, (2-1,)
, (2-2) is a chattering removal circuit, (20-]),
(20-2) is a gate circuit, (50) is a #1 control unit, (60) is a #2 control unit, and (1,00) is an operation display.

The operation shown in FIG. 5 will be explained. The selection switch (1) is a selection switch for selecting either the #1 control unit (50) or the #2 control unit (60) to transmit a digital signal to the operation display (100). The figure shows a state in which a selection control signal, which is a ground signal, is supplied from the selection switch (1) to the gate circuit (20-1) via the chattering removal circuit (2-). When the gate circuit (20-1) is driven, it connects the digital signal path between the #1 control unit (50) and the operation display (100), allowing bidirectional transmission of dental signals.

FIG. 6 is a diagram showing a configuration example of a numerical control device,
In the figure, (50) is #1 control unit, (70) is servo amplifier, (80) is servo motor, (90-1)
-(90-3) are inter-unit cables, and (1,00) are operation indicators. The #1 control unit (50) is connected to the operation display (100) and the servo amplifier (70) by inter-unit cables (90-1, ) and (90-2), and the servo amplifier (70) is further connected to the cable(
90-3) is connected to the servo motor (80). Additionally, the #1 control unit (50) has built-in carts such as a microprocessor (hereinafter referred to as CPU) cart (51), a memory card (52), a machine control card (53), and a board control car F (54). There is. #2 control unit (60) is also constituted by a similar card.

[Problem to be solved by the invention] The conventional control unit selection circuit as described above handles only digital signals (usually OV or +5V TTL level dental signals) and uses a semiconductor case as a circuit switching element.・Elements were used. Therefore, is there any problem when selecting one of the multiple control units and transmitting the dental signal between it and the operation display, or is there a problem that only analog signals such as video signals can be selected? Ta. For example, the operation display often has a built-in image display such as a CRT, and if you want to select one of multiple control units and beautifully switch the image information transmitted from the selected control unit. Another problem was that the switching timing between the synchronization signal and the video signal was inappropriate and unsatisfactory.

This invention has been made to solve such problems, and it enables the selection and switching of both digital signals and analog signals, and also improves the switching timing of both signals, so that when switching the selection of the video signal, An object of the present invention is to obtain a control unit selection circuit capable of beautifully switching images displayed on a CRT.

[Means for Solving the Problems] A control unit selection circuit according to the present invention is a control unit selection circuit that selects one of a plurality of control units and connects it to a common operation display. a selector that generates a selection signal for selecting one of the control units; a first delay circuit that delays the selection signal output from the selector for a certain period of time and outputs the delayed selection signal as a first selection control signal; a second delay circuit that further delays the first selection control signal output from the first delay circuit for a certain period of time and outputs the delayed signal; and a selection signal output from the selector and the second selection control signal. an AND circuit that calculates an AND with a delay signal output from the delay circuit and outputs the result of the operation as a second selection control signal; and an operation display common to the control unit and the operation display for each of the plurality of control units. a digital signal switch that is provided in a digital signal path between the devices, is selectively driven by a first selection control signal output from the first delay circuit, and opens and closes the digital signal path; and the plurality of control units. provided in the analog signal path between the control unit and the common operation display for each time, and selectively driven by a second selection control signal output from the AND circuit,
and an analog signal switch that opens and closes the analog signal path.

[Operation] In the present invention, the first selection control signal outputs the selection signal output from the selector via the first delay circuit, thereby reducing the digital signal between the selected control unit and the common operation display. connection. In addition, a logical product signal of a further delayed signal outputting the first selection control signal via a second delay circuit and the selection signal output from the selector is used as a second selection control signal to control the selected control signal. Connect the analog signal path between the unit and the common operation display.

Next, when disconnecting the connected circuit, immediately disconnect the analog signal path from the control unit that has been selected by the non-selection signal output from the selector, and also send the non-selection signal through the first delay circuit. The delayed non-selection signal acts to disconnect the digital signal path from the previously selected control unit.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the selection control signal generation circuit of the present invention, in which (1-1) is a selection switch, (2)
-1), (2-2) -(2-n) are chattering removal circuits, (3-1), (3-2) -(3-n) are first delay circuits, (4-1), (4-2)...(4-n
) is the second delay circuit, (5-1), (5-2)-(5
-n) is an AND circuit, (11, -1), (II-2),
(+2-]), (12-2)-(In-1), (1,n
-2) is a terminal.

The operation shown in FIG. 1 will be explained. Now select switch (1-1,
) or #1 control unit is selected. Input the ground signal (OV) from the selection switch (1-]) to the chattering removal circuit (2-1,), and
-1), the chatter link is removed and the output signal is the first
The signal is supplied to the delay circuit (3-1) and the AND circuit (5-1). The first delay circuit (3-1) outputs a signal obtained by delaying the input signal by a time t, and supplies it to the outside as a first selection control signal for the first control unit from a terminal (+1-1.). At the same time, it is supplied to the second delay circuit (4-1). The second delay circuit (4-1) outputs a signal obtained by delaying the input signal by a time t, and supplies the signal to the AND circuit (5-1,). The AND circuit (5-1) performs an AND operation on two signals input from the chattering removal circuit (2-1) and the second delay circuit (41), and sends the result of the operation to the terminal (If
-2) is supplied to the outside as a second selection control signal for the first control unit.

As a specific example of application, for example, when selectively connecting CRT-related signals from the first control unit to an operation display unit with a CRT, the vertical synchronization signal and horizontal synchronization signal of the CRT may be selected using the selection control signal in the first clause 1. Then, the video signal is selectively connected by a second selection control signal delayed for a certain period of time.

In this way, by selectively connecting the synchronization signal, which is a digital signal, and the video signal, which is an analog signal, with a time difference, it is possible to change the CRT screen beautifully.

FIG. 2 is a detailed circuit diagram of one system of the selection control signal generation circuit of FIG. 1, in which (1) is a selection switch, (2) is a chattering removal circuit, (3) is a first delay circuit, 4) is the second delay circuit, (5) is the AND circuit, (6-1) to (
6-6) is an inverter, (7) is an AND gate, (8-
1) ~ (8-4) are resistors, (9-], ) ~ (9-3)
is a capacitor, and (10-1) and (10-2) are terminals.

FIG. 3 is a waveform diagram for explaining the operation of FIG. 2.

The operation of FIG. 2 will be explained with reference to FIG. When the selection switch (1) is not selected, the circuit is open, and when it is selected, the circuit is closed. If the selection switch (1) is now selected, the ground signal is input to the chattering removal circuit (2). The chattering removal circuit (2) includes an inverter ([1-1), a resistor (81), (8-2),
It is composed of a capacitor (9-1) and serves as an integrating circuit. Therefore, the selection switch (1) shown in FIG.
The chattering is removed from the output signal of ), and the output signal of the chattering removal circuit (2) shown in FIG. The output signal of the chattering removal circuit (2) is supplied to a first delay circuit (3) and an AND circuit (5). The first delay circuit (3) is composed of an integrator circuit consisting of a resistor (8-3) and a capacitor (9-2), and an inverter (6-2), and a delay time 11 occurs between signal input and output. Then, the signal is inverted by the inverter (6-2). Figure 3 (1) shows the input signal of the inverter (B-2) which is the output of the integrating circuit, and the input signal of the inverter (B-2) which is the output of the integrating circuit.
) shows the first selection control signal, which is a Low Active signal output from the first delay circuit (3) to the terminal (10-1). The output signal of the first delay circuit (3) is output to the terminal (1O-1) and is also output to the inverter ([1
-3) to the second delay circuit (4). The second delay circuit (4) has the same configuration as the first delay circuit (3), and similarly generates a delay time t2 and inverts the signal between the input and output of the signal. The output signal of this second delay circuit (4) is shown in FIG. The second delay circuit (
The output signal of 4) is input via an inverter (6-5) to one input terminal of an AND circuit (5) or a built-in AND gate <7). Since the output signal of the chattering removal circuit (2) has already been input to the other input terminal of the AND gate (7), the AND gate (7) calculates the logical product of both signals, and the result of this operation is set to Low. Active
In order to make the e signal, the terminal (
10-2) is output as the second selection control signal. This second;j1 selection control signal is shown in FIG. 3(g).

Next, if the circuit of the selection switch (1) is opened and it is no longer selected, the chattering removal circuit (2), the first delay circuit (3), and the second delay circuit (4) each have built-in circuits. Integrating circuit capacitor (9-1), (
9-2), the charge accumulated in (9-3) is discharged,
The signal is inverted after the output voltage of the integrating circuit becomes below the threshold level of the inverter connected to the next stage. Therefore, a certain delay time occurs after the selection switch (1) circuit is opened until each signal is inverted. Now, in the first delay circuit (3), the time t 1 second
It is assumed that a delay time of time t4 occurs in the delay route (4).

This state is shown in FIGS. 3(A) to 3(G).

Now, if we consider the output signal of the chattering removal circuit (2) shown in FIG. 3 (a) as a temporal reference signal, the first selection control signal output from the terminal (10-1) It becomes valid after a delay of t1, and the time t is greater than the reference signal.
It becomes invalid after 3 delays. Generally, the time relationship between the two is t >
t 3. This is to first open the signal path from the previously selected control unit during the transient period of selection switching, and then close the signal path from the newly selected control unit. Further, the second selection control signal outputted from the terminal (10-2) becomes valid after a time delay of t+t2 from the reference signal, and becomes invalid at the same time as the reference signal without any time delay. Therefore, the valid time of the second selection control signal always exists within the valid time of the first selection control signal.

FIG. 4 is a block diagram showing an embodiment of the control unit selection circuit of the present invention, in which (1) is a selection switch, (2-
1), (2-2) are chattering removal circuits, (3-1
), (3-2) is the first delay circuit, (4-1), (
4-2) is a second delay circuit, (5-1) and (5-2) are AND circuits, (201) and (20-2) are gate circuits,
(21-1), (21-2) are relays, (22-1),
(22-2) and (22-3) are data buffer circuits, (
23-1), (23-2), and (23-3) are connectors for connecting cables, and (30) is a selection control signal generation circuit.

The operation shown in FIG. 4 will be explained. In the figure, the selection control signal generating circuit (30) is the same as the circuit already explained in FIGS. 1 and 2. Assuming that the selection switch (1) is now set to select the #1 control unit, the first
The delay circuit (3-1) outputs the #] first selection control signal for the control unit to drive the gate circuit (20-1,). When the gate circuit (20-1) is driven, #1
From the control unit connector (23-]) to the operation display connector (23-3) via the data buffer circuit (22-1,), gate circuit (20-1,), and data buffer circuit (22-3). The bidirectional digital signal paths leading to the two devices are connected, and it is possible to send and receive digital signals (for example, TTL level OV or +5■ digital signals) between the two devices. After that, after a certain period of time has passed, # is output from the AND circuit (5-1).
The second selection control signal for the first control unit is output and drives the relay (21-1). When the relay (21-1) is driven, an analog signal path is connected from the #1 control unit connector (23-1) to the operation display connector (23-3>), making it possible to transmit analog signals. Next, if the selection switch (1) is switched to select the #2 control unit, the second selection control signal for the #1 control unit will immediately become invalid, stop driving the relay (21-1), and then After a certain period of time has elapsed, the first selection control signal for #1 control unit becomes invalid, and Case 1/Circuit (20-1)
Stops driving. Similarly, the first
The selection control signal is switched to the selection switch (1) or the #2 control unit side, and after a certain period of time has passed and the old first selection control signal for the #1 control unit becomes invalid, the second selection control signal is switched to the #2 control unit side.
A valid signal is output from the delay circuit (3-2) to drive the gate circuit (20-2).

After that, after a certain period of time has passed, #2 is output from the AND circuit (5-2).
The second selection signal for the control unit is output and the relay (21-
2) Drive. As a result, digital data and analog signals can be transmitted between the #2 control unit and the operation display. Moreover, the switching selection of the signals between the first control unit and the second control unit is performed smoothly, and the CR between the operation displays is
Even when a T is built in, display images can be switched beautifully.

Also, even if there are two or more control units, the first
One of them can be similarly selected by using the selection switch (1-1) shown in the figure or by combining changeover switches in a tree shape.

In addition, in this embodiment, the chattering removal circuit and the first delay circuit were described as separate circuits, but since the delay circuit or the built-in integrating circuit has a chattering removal function, the chattering removal circuit is omitted to simplify the circuit. A selection circuit may also be used.

Therefore, a chatter elimination circuit is not a necessary condition of the present invention.

In addition, in this embodiment, all digital signals input and output to the gate circuit are connected via the data buffer circuit, but this means that the connection cable between the control unit and the operation display is relatively small. This is because a data buffer circuit is generally used to stabilize operation when the signal transmission method is long and the signal transmission method directly transmits TTL level signals. If the control unit and operation display are close together and the connection cable is short, or if the signal transmission methods are different, the data buffer circuit may not be used. For example, if the signal transmission method is a differential transmission method or an optical fiber transmission method, a data buffer circuit is not required. Therefore, a data buffer circuit is also not a requirement of the present invention.

Further, in this embodiment, an example has been described in which a relay is used as a circuit opening/closing element for an analog signal, but the circuit opening/closing element is not limited to a relay, and a semiconductor analog switch circuit may be used.

Furthermore, in this embodiment, the first delay circuit (2-1)
, (2-2) and the second delay circuit (3-1), (3
-2) have been explained so that the number of timing control circuits corresponding to each control unit is provided, or only one set of these timing control circuits is provided in common, and the timing control signal output from this common circuit and the selection for each control unit are provided. The actual selection control signal may be generated by performing an AND operation with the signal. In this case, the timing control circuit is simplified, resulting in an economical circuit as a whole.

[Effects of the Invention] As described above, according to the present invention, digital signal paths and analog signal paths from a plurality of control units can be selectively opened and closed with time differences and connected to a common operation display. Because of this structure, for example, even if two or more numerical control devices are installed on a production line, it is possible to control operations and check the status of each control unit using one common operation display, making the entire device cheaper. It has an economic effect.

Also, when image information is switched and displayed on the operation display, the images displayed on the CRT can be switched beautifully, which has the effect of improving the image quality when switching images on the operation display.

Furthermore, since the number of selectable control units can be increased arbitrarily by connecting signal path switching circuits in parallel or cascade, the system can be easily expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the selection control signal generation circuit of the present invention, FIG. 2 is a detailed circuit diagram of one system of the selection control signal generation circuit of FIG. 1, and FIG. 4 is a block diagram showing an embodiment of the control unit selection circuit of the present invention, FIG. 5 is a block diagram of a conventional control unit selection circuit, and FIG. 6 is a numerical control It is a figure showing an example of composition in an apparatus. In the figure, (1) and (1-1) are selection switches, (
2) , (2-1) to (2-n) are chattering removal circuits, (3) , (3-1) to (3-n) are first delay circuits, (4), (4-1) ~(4-n) is a second delay circuit, (5), (5-1,)-(5-n) is an AND circuit,
(B-1-)-(B-6) are inverters, (7) are AN
D gate, (8-1) to (8-4) are resistors, (9-1
) to (9-3) are capacitors, (10-1), (to-
2), (11-1)-(in-2) is a terminal, (20-1
), (20-2) are gate circuits, (2+, -1), (2
1-2) is a relay, (22-1) to (22-3) are data buffer circuits, (23-1) to (23-3) are connectors, (30) is a selection control signal generation port, (5o) is #1 control unit, (60) is #2 control unit, (70) is servo amplifier, (80) is servo motor, (90-1,
) to (90-3) are inter-unit cables, and (100) is an operation display. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] A control unit selection circuit that selects one of a plurality of control units and connects it to a common operation display, generating a selection signal that selects one of the plurality of control units. a first delay circuit that delays a selection signal output from the selector for a certain period of time and outputs it as a first selection control signal; a second delay circuit that further delays the selection control signal for a certain period of time and outputs the delayed signal; and a logical product of the selection signal output from the selector and the delay signal output from the second delay circuit. an AND circuit that performs a calculation and outputs the calculation result as a second selection control signal;
a digital signal switch that is selectively driven by a first selection control signal output from a delay circuit and opens and closes the digital signal path; and a digital signal switch for each of the plurality of control units between the control unit and the common operation display. and an analog signal switch which is provided in the analog signal path of the circuit, is selectively driven by a second selection control signal output from the AND circuit, and opens and closes the analog signal path. selection circuit.