JPS60111546A - Communication system between processors - Google Patents

Communication system between processors

Info

Publication number
JPS60111546A
JPS60111546A JP58219227A JP21922783A JPS60111546A JP S60111546 A JPS60111546 A JP S60111546A JP 58219227 A JP58219227 A JP 58219227A JP 21922783 A JP21922783 A JP 21922783A JP S60111546 A JPS60111546 A JP S60111546A
Authority
JP
Japan
Prior art keywords
data
processor
driver
effective
processor unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58219227A
Other languages
Japanese (ja)
Inventor
Masanori Kakimoto
柿本 正憲
Mitsuo Ishii
石井 光雄
Hiroaki Ishihata
石畑 宏明
Keiji Sato
恵司 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58219227A priority Critical patent/JPS60111546A/en
Publication of JPS60111546A publication Critical patent/JPS60111546A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To improve the operating rate of the entire system by arranging one data driver per processing unit to reduce remarkably the delay in data propagation. CONSTITUTION:Six drivers (f) on a data passing path are disconnected at normal operation to make a driver (g) in a processing device C effective. When the processor C is on the midway path of the communication between remote processors, the device C disconnects the driver (g) and makes one of the 6 drivers (f) effective to pass the data without intervention of the processor C afterward. In making two independent buses as right/left to upper/lower buses and lower/left to upper/right buses effective, the 2-channel data are transmitted at the same time.

Description

【発明の詳細な説明】 (11発明の技術分野 本発明はプロセッサ間通信方式に係り、特に格子状に結
合した複数プロセッサ間の通信を途中のプロセッサに設
けたデータ通過バスを有効に使うことにより速やかにデ
ータ転送を行なう方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to an inter-processor communication system, and in particular, to communication between a plurality of processors connected in a grid by effectively using a data passing bus provided in an intermediate processor. It relates to a method for quickly transferring data.

(2)従来技術と問題点 従来、多数の処理プロセッサユニットを並べ、並列動作
を行なうことにより演算速度を向上させる方式がある。
(2) Prior Art and Problems Conventionally, there is a method of arranging a large number of processor units and performing parallel operations to improve calculation speed.

けれど該従来方式では各プロセッサユニットが完全に独
立に動作することを条件へすると、適用し得る問題が非
常に限定されたものとなるため、異なるプロセッサユニ
ット間を何らかの形で結合して情報の交換を行なうこと
は不可欠と言ってよい。これまで考えられている基本的
な結合形態には2つの方式がある。それらは、■すべて
のプロセッサユニットに共通なパスをもつ方式■マトリ
ックス状(格子状)にプロセッサユニットを配置し各プ
ロセッサユニットが隣接プロセッサユニットとそれぞれ
直接にデータを転送するような通信パスを持つ方式であ
る。実際にはこれらを組合わせたり、種々の変形・改良
を施した方式が考えられている。■には、共通パスにア
クセスが集中するためユニット数が10台程度に限定さ
れるという欠点があり、■には、遠方のユニットと通信
を行なう際に途中の多くのユニットを通過しなければな
らず通信速度が遅いという欠点がある。
However, in this conventional method, if each processor unit is required to operate completely independently, the applicable problems are extremely limited, so it is necessary to connect different processor units in some way to exchange information. It can be said that it is essential to do so. There are two basic types of coupling that have been considered so far. These are: ■ A method in which all processor units have a common path. ■ A method in which processor units are arranged in a matrix (lattice) and each processor unit has a communication path that directly transfers data with its neighboring processor units. It is. In reality, systems that combine these methods or make various modifications and improvements are being considered. (2) has the disadvantage that the number of units is limited to about 10 because access is concentrated on the common path, and (2) requires passing through many units on the way when communicating with distant units. However, the disadvantage is that the communication speed is slow.

(3)発明の目的 本発明は前記欠点に鑑みて、゛個々のプロセツサユニッ
ト内に、データ通過用の6本のパスを設け、遠方プロセ
ッサユニット間で通信を行なう場合に、データが通過す
る途中のプロセッサユニ・ノドでは、該データ通過用パ
スを使うことにより、途中のプロセッサユニットの処理
に影響を与えることなく、4デ一タ転送速度の向上を図
ることを目的とする。
(3) Purpose of the Invention In view of the above-mentioned drawbacks, the present invention provides six paths for data passage in each processor unit so that data can pass when communicating between distant processor units. The purpose of this is to improve the 4-data transfer speed by using the data passing path in the intermediate processor units without affecting the processing of the intermediate processor units.

(4)発明の構成 該目的は、格子状に結合した複数のプロセッサユニット
から構成されるデータ通信システムにおいて、離れたプ
ロセッサユニット間でデータ転送を行なう場合に、送信
途中で通過するプロセッサユニットに6本のデータ通過
パスを備え、該データ通過パスの1本又は2本を組合せ
て任意方向へのデータ転送を行なう手段を設けたことを
特徴とる。
(4) Structure of the Invention The object of the present invention is to provide a data communication system consisting of a plurality of processor units connected in a grid, in which when data is transferred between distant processor units, a The present invention is characterized in that it includes a book data passing path, and means for transferring data in any direction by combining one or two of the data passing paths.

第1図は本発明の一実施例を示す全体の結合形態を示す
図である。
FIG. 1 is a diagram illustrating an overall connection form showing an embodiment of the present invention.

図において、1は通信路、11〜nnはプロセッサユニ
ットである。
In the figure, 1 is a communication path, and 11 to nn are processor units.

第2図は本発明の一実施例を示すプロセッサユニットの
詳細を示す図である。
FIG. 2 is a diagram showing details of a processor unit showing an embodiment of the present invention.

図において、Cは従来のプロセッサユニット。In the figure, C is a conventional processor unit.

dは本発明のプロセッサユニット eはデータ通過用パ
ス(上下左右から2つを選ぶすべての組合せを用意し、
全部で6本備える。)、fはデータ通過パスのドライバ
、gはデータドライバ(従来からある。)さて、プロセ
ッサユニットCは、データドライバg、データ通過パス
のドライバfの合計10個のドライバの開閉およびデー
タ転送方向の制御を行なう。
d is a processor unit of the present invention; e is a data passing path (all combinations of two selected from top, bottom, left, and right are prepared;
There are 6 pieces in total. ), f is a data passing path driver, and g is a data driver (conventional).Now, the processor unit C controls the opening/closing of a total of 10 drivers, data driver g, and data passing path driver f, and the direction of data transfer. control.

通常の動作においては、データ通過用パスのドライバf
を6つとも切断しておき、プロセッサユニットC内ドラ
イバgを有効にしておく。この場合はプロセッサユニッ
トCの部分だけで動作することになる。次にデータ通過
モードであるが、当該プロセッサユニットCが遠方プロ
セラ号ユニット間通信の途中経路になるような場合7ま
ず外部から当該プロセッサユニットCにデータ通過モー
ドにするよう要求が送られてくる。該要求を受けつける
と、プロセッサユニットCは、ドライバgを切断し、デ
ータ通過パスのドライバfの6つのドライバのうち1つ
を有効とすることにより、以後はプロセッサユニットC
が介入することなくデータを通過させることができる。
In normal operation, the data passing path driver f
All six are disconnected, and the driver g in the processor unit C is enabled. In this case, only the processor unit C will operate. Next, regarding the data passing mode, if the processor unit C becomes an intermediate route for communication between distant processor units, a request is first sent from the outside to the processor unit C to set it to the data passing mode. Upon receiving the request, the processor unit C disconnects the driver g and enables one of the six drivers of the data passing path driver f.
data can pass through without intervention.

また、上−下に対して左−右、上−右に対して下−左と
いうように独立した2つのパスを有効にすれば、同時に
2チヤンネルのデータ通過を行なうことができる。
Furthermore, if two independent paths are enabled, such as left-right for top-bottom and bottom-left for top-right, data can be passed through two channels at the same time.

あるいは上−下、上−右、上−左というような一方向か
ら出る複数のパスを有効にすれば、一方向から同時に多
方向へデータを通過させることができる。さらに、通過
データが入ってくる方向のプロセッサユニットC内ドラ
イバgを有効にしてプロセッサユニットCにもそれを取
り込めば、データ通過用パスeを通過中のデータを富に
監視することも可能である。
Alternatively, by enabling multiple paths from one direction, such as top-bottom, top-right, top-left, data can pass from one direction to multiple directions at the same time. Furthermore, by enabling the driver g in the processor unit C in the direction in which passing data comes in and importing it into the processor unit C, it is also possible to closely monitor the data passing through the data passing path e. .

(6)発明の詳細 な説明した様に、本発明によれば従来は途中のプロセッ
サユニットによる読み書きを連結させて順次転送を行な
う方式が、■プロセッサユニットにつき1個のデータド
ライバを並べるだけになるのでデータ伝播の遅れは飛躍
的に軽減される。
(6) As described in detail, according to the present invention, the conventional method of sequentially transferring data by linking reads and writes by processor units in the middle can be reduced to ■ arranging one data driver per processor unit. Therefore, delays in data propagation are dramatically reduced.

必要がな(、独立に別の処理を行なわせることができる
ので、システム全体の稼働率も向上する。
Since other processing can be performed independently, the operating rate of the entire system also improves.

また、種々の組合せの通過方向を選択することができ、
通過データを監視することもできるため、柔軟性のある
利用法が可能である。
In addition, various combinations of passing directions can be selected,
Passage data can also be monitored, allowing for flexible usage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す全体の結合形態を示す
図である。 第2図は本発明の一実施例を示すプロセッサユニットの
詳細を示す図である。 記号の説明、Cは従来のプロセッサユニット。 dは本発明のプロセッサユニット、eはデータ通適用パ
ス(上下左右から2つを選ぶすべての組合せを用意し、
全部で6本備える。)、fはデータ通過パスのドライバ
、gはデータドライバ。 し1.・昂 茅 I K
FIG. 1 is a diagram illustrating an overall connection form showing an embodiment of the present invention. FIG. 2 is a diagram showing details of a processor unit showing an embodiment of the present invention. Explanation of symbols: C is a conventional processor unit. d is a processor unit of the present invention, e is a data communication application path (all combinations of two selected from top, bottom, left and right are prepared,
There are 6 pieces in total. ), f is a data passing path driver, and g is a data driver. 1.・Kokai IK

Claims (1)

【特許請求の範囲】[Claims] 格子状に結合した複数のプロセッサユニットから構成さ
れるデータ通信システムにおいて、離れたプロセッサユ
ニット間でデータ転送を行なう場合に、送信途中で通過
するプロセッサユニットに6本のデータ通過パスを備え
、該データ通過バスの一本又は2本を組合せて任意方向
へのデータ転送を行なう手段を設けたことを特徴とする
プロセッサ間通信方式。
In a data communication system consisting of a plurality of processor units connected in a grid, when data is transferred between distant processor units, six data passing paths are provided in the processor units through which the data is transmitted. An inter-processor communication system characterized by providing means for transferring data in any direction using one or a combination of two transit buses.
JP58219227A 1983-11-21 1983-11-21 Communication system between processors Pending JPS60111546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58219227A JPS60111546A (en) 1983-11-21 1983-11-21 Communication system between processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58219227A JPS60111546A (en) 1983-11-21 1983-11-21 Communication system between processors

Publications (1)

Publication Number Publication Date
JPS60111546A true JPS60111546A (en) 1985-06-18

Family

ID=16732189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58219227A Pending JPS60111546A (en) 1983-11-21 1983-11-21 Communication system between processors

Country Status (1)

Country Link
JP (1) JPS60111546A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364178A (en) * 1986-08-29 1988-03-22 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Image processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364178A (en) * 1986-08-29 1988-03-22 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Image processing system

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