JPH08297651A - Array processor - Google Patents

Abstract

PURPOSE: To considerably increase the number of processor elements which can be simultaneously communicated in the longitudinal and lateral directions of the array processor. CONSTITUTION: This array processor is provided with a data communication network 1 which is formed by connecting plural longitudinal direction and laterial direction buses 2a and 2b in the from of matrix, plural processor elements PE each connected to intersection 3 of the longitudinal direction and lateral direction buses 2a and 2b, plural switches 4 each interposed between the intersections 3, and controller 5 for controlling the opening/closing operations of the plural switches 4 and by electrically and arbitrarily disconnecting among the intersections 3, the array processor can be independently used for each desired block of the longitudinal direction and laterial direction buses 2a and 2b. Thus, data can be simultaneously transmitted/received in the plural blocks at the same row and the same column in the data communication network 1 constituted in the form of matrix.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array processor, and more particularly to a single-instruction multiple data type (SIM) in which a large number of processor elements are connected in a grid on a single LSI.
It is suitable for use in a D-type) array processor.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, a large number of processor elements PE (processor elements) are provided in an array, and parallel processing is performed by each of these many processor elements PE, whereby the processing speed can be increased. Such an array processor has been proposed. In order to realize such parallel operation, SIMD is used for processing control.
There is one that uses control of the type (single instruction multiple data type).

This SIMD type control is such that all processor elements PE process the same instruction. That is, in the SIMD type array processor, a common control signal line is connected to each processor element PE, and one processor element PE is connected to each processor element PE via this control signal line.
By sending one instruction, each processor element PE
The same command is processed in.

Further, the data operated in parallel by each processor element PE is successively collected in other processor elements PE via a vertical global bus and a horizontal global bus which are connected in the vertical and horizontal directions, respectively. It is designed to be followed. A local bus is provided to communicate with the adjacent processor element PE.

[0005]

As described above, the SI
In the MD type array processor, the control signal line is common to all the processor elements PE, and the processed data is transmitted via the common vertical global bus and horizontal global bus.

Therefore, even if a plurality of processor elements PE are connected in the vertical and horizontal directions, respectively, the processor elements PE capable of simultaneous communication are limited to two processor elements PE (one set of processor elements PE). Therefore, there is a problem that other processor elements PE connected to the same row (or the same column) as these two processor elements PE cannot perform data communication.

The present invention has been made to solve such a problem, and it is possible to significantly increase the number of processor elements capable of simultaneously communicating in the vertical and horizontal directions. To aim.

[0008]

The array processor of the present invention comprises a data communication network in which a plurality of vertical buses and horizontal buses are connected in a matrix, and an intersection of the vertical buses and the horizontal buses. A plurality of processor elements connected to each other, a plurality of switches interposed between the intersections, and a controller for controlling opening / closing operations of the plurality of switches.

Another feature of the present invention is that the control device includes a pattern generation circuit for generating a switch opening / closing pattern for opening / closing each of the plurality of switches according to a predetermined pattern.

[0010]

Since the present invention has the above-mentioned technical means, it is electrically isolated between the intersections at which the switches are turned off, so that it is partitioned by the switches in the off state in the vertical bus and the horizontal bus. The parts can be used independently. As a result, it is possible to simultaneously transmit and receive a plurality of data in the same row and the same column in the data communication network configured in a matrix, and when transmitting and receiving data between the processor elements PE, the vertical direction is used. The use efficiency of the bus and the lateral bus can be significantly improved.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one block in the array processor of this embodiment.

In FIG. 1, 1 is a data communication network, 2a is a vertical bus, 2b is a horizontal bus, 3 is an intersection, 4 is a switch, 5 is a controller, and 6 is a pattern generation circuit. In the case of the present embodiment, the data communication network 1 is configured by connecting six vertical buses 2a and horizontal buses 2b in a matrix form, and transmits / receives data processed by the processor element PE. It is used to

Each processor element PE is connected to an intersection 3 of the vertical bus 2a and the horizontal bus 2b, and in this embodiment, 6 in the vertical direction and 6 in the horizontal direction. Although an example in which a total of 36 processor elements PE are arranged is shown, in actuality, an array processor is configured by connecting several tens or more processor elements in both the vertical and horizontal directions.

Each processor element P connected in this way
The E processes data in the array processor by transmitting / receiving data to / from other processor elements PE via the vertical bus 2a and the horizontal bus 2b.

The switch 4 is interposed between the intersections 3 and 3. When the switch 4 is in the open state, the space between the intersections 3 and 3 is opened. 2a or lateral bus 2b is switch 4 open
It will be in a state of being independent from each other across.

Further, when the switch 4 is in the closed state, the space between the intersections 3 and 3 is closed, so that data is transmitted and received through the vertical bus 2a or the horizontal bus 2b.

Since data is transmitted / received in this manner, in the array processor of this embodiment, data can be transmitted / received in various modes by controlling the on / off state of the switch 4. become.

That is, as described above, conventionally, only one type of communication can be simultaneously performed with one data line. Therefore, for example, a certain lateral bus 2b
When data is transmitted / received by a pair of adjacent processor elements PE (also in the case of the vertical bus 2a), conventionally, the other four processor elements PE must wait during that time. It was

However, in the array processor of this embodiment, all the processor elements PE related to the horizontal bus 2b can simultaneously send and receive data between adjacent processor elements. That is, in such a case, the on / off control of the switches 4a to 4e related to the lateral bus 2b is performed using the first pattern shown in Table 1 below.

[0020]

[Table 1]

That is, as is clear from Table 1, the first
According to this pattern, the first switch 4a is turned on and the second switch 4a is turned on.
Switch 4b is off, the third switch 4c is on, the fourth switch 4d is off, and the fifth switch 4e is on.

Therefore, in this case, the first processor element a and the second processor element b are connected via the first switch 4a. Further, the third processor element c and the fourth processor element d are connected via the third switch 4c. Further, the fifth processor element e and the sixth processor element f are connected via the fifth switch 4e.

In this way, adjacent processor elements are connected to each other and the second switch 4b is connected.
And since the fourth switch 4d is off, each processor element connected as a set becomes independent from the processor elements of the other set.

Therefore, since three sets of processor elements related to the same horizontal bus 2b can simultaneously perform data communication, the communication time required for data transmission / reception can be greatly shortened.

As a result of transmitting / receiving data while performing the on / off control of the switch 4 according to the first pattern,
It is assumed that the data is aggregated in the second processor element b, the fourth processor element d, and the sixth processor element f.

In this case, on / off control of the switch 4 is then performed using the fifth pattern. That is, the first switch 4a is turned off, the second switch 4b is turned on,
The third switch 4c is turned on, the fourth switch 4d is turned off, and the fifth switch 4e is turned off.

In this way, the data of the second processor element b is collected in the fourth processor element d,
The data of the sixth processor element f is aggregated in the eighth processor element (not shown), and the data for four processor elements is aggregated in one processor element only by transmitting and receiving the data twice. It

Hereinafter, by performing on / off control of the switch 4 in the above-described pattern, one processor element PE includes 8 → 16 → 32.
・ The data of and can be aggregated.

FIG. 2 shows an example of the processor element PE. The processor element PE includes an input terminal 20, an arithmetic logic unit (ALU) 21, a register 22, and an output terminal 2.
3, and image data (for one pixel) from an optical sensor (not shown) is input through the input terminal 20.

The image data input from the photosensor is given to the arithmetic logic unit 21 and subjected to a predetermined process, and the processing result is stored in the register 22. Further, it is output to the adjacent processor element PE via the output terminal 23.

Further, image data from the adjacent processor element PE is input through the input terminal 20, and this image data is also given to the arithmetic logic unit 21 in the same manner as the image data input from the above-mentioned photosensor to perform a predetermined processing. Is done
The processing result is stored in the register 22.

That is, the processor element P shown in FIG.
E has a function of performing a predetermined process on the image data input from the corresponding optical sensor and performing a predetermined process on the image data input from the adjacent processor element PE and outputting the image data.

As described above, the processing speed can be improved by processing the image data on the array processor and then outputting it to the outside. Moreover, in the case of the array processor of this embodiment, the vertical bus 2a and the horizontal bus 2 are used when transmitting / receiving data between the processor elements PE.
Since the usage efficiency of b can be greatly improved, the data processing speed and processing amount on the array processor can be greatly improved.

[0034]

As described above, the present invention is connected to a data communication network in which a plurality of vertical buses and horizontal buses are connected in a matrix and to the intersections of the vertical buses and the horizontal buses. Since the plurality of processor elements, the plurality of switches interposed between the intersections, and the control device for controlling the opening / closing operation of the plurality of switches are provided, the state of the switches is turned off. Since the intersections are electrically disconnected from each other, the sections of the vertical bus and the horizontal bus divided by the switch in the off state can be used independently. As a result, it becomes possible to simultaneously transmit and receive a plurality of data in the same row and the same column in a data communication network configured in a matrix, and when transmitting and receiving data between processor elements, a vertical bus is used. The use efficiency of the horizontal bus can be greatly improved, and the data processing speed and the data processing amount on the array processor can be significantly improved.

According to another feature of the present invention, the control device is provided with a pattern generating circuit for generating a switch opening / closing pattern for opening / closing a plurality of switches in accordance with a predetermined pattern. In this case, the on / off control of the switch can be performed immediately and easily, and the data processing speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an array processor of the present invention.

FIG. 2 is a block diagram illustrating an example of a processor element.

FIG. 3 is a block diagram showing an overall configuration of a conventional array processor.

[Explanation of symbols]

 1 Data Communication Network 2a Vertical Bus 2b Horizontal Bus 3 Intersection 4 Switch 5 Controller 6 Pattern Generation Circuit

Claims (2)

[Claims] 1. A data communication network in which a plurality of vertical buses and horizontal buses are connected in a matrix, and a plurality of processor elements respectively connected to the intersections of the vertical buses and the horizontal buses, A plurality of switches provided between the intersections and the controller for controlling the opening / closing operation of the plurality of switches in order to connect and disconnect the intersections. A featured array processor. 2. The array processor according to claim 1, wherein the control device includes a pattern generation circuit that generates a switch opening / closing pattern for opening / closing each of the plurality of switches according to a predetermined pattern. .