JP3180697B2 - Undershoot overshoot prevention circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a waveform input circuit, and more particularly to a method for removing noise.

[0002]

2. Description of the Related Art Conventionally, this type of waveform input circuit has been provided with a clamp diode for removing noise, thereby preventing overshoot and undershoot.

[0003]

However, in the conventional waveform input circuit including only the clamp diode, the slew rate of the input waveform cannot be adjusted, and the input waveform has a sharp rise or a sharp fall. In the case of a waveform, there is a problem that crosstalk occurs between leads in an LSI.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to adjust a slew rate of an input waveform and increase a delay time even when a steep waveform is input. It is another object of the present invention to provide an undershoot overshoot prevention circuit that prevents crosstalk between leads in an LSI.

[0005]

In order to achieve the above object, an undershoot / overshoot prevention circuit according to the present invention comprises, as a transmission path from an input terminal of an input signal to a waveform input section, a path to which a capacitive component is added or Sutra not added
First and second selecting means for switching and selecting a road,
The first selection means has an input terminal connected to the input terminal,
The second selection means has an input terminal connected to the output of the first selection means.
And a buffer circuit and an inverter circuit which are connected to one end and an output terminal of which is connected to the waveform input section and commonly receive the output of the second selecting means , and differentiate the outputs of the buffer circuit and the inverter circuit, respectively. first and second <br/> differentiating circuit comprises, out of the first and second differentiating circuit
And a selection signal of the first and second selection means, respectively.
The first selection means and the second selection means respond to steep rising and falling input signal waveforms.
An undershoot overshoot prevention circuit characterized in that the input signal waveform is dulled and transmitted to the waveform input section by switching and selecting a path to which a capacitive component is added .

[0006]

Embodiments of the present invention will now be described with reference to the drawings. In a preferred embodiment of the present invention, a signal from an input terminal (100 in FIG. 1) is input to a first terminal, and is applied to one of a second terminal and a third terminal based on a logical value of a first selector signal. A first selector (101) for selecting and outputting, and a first selector (101 in FIG. 1)
The second and third terminals are connected to the second and third terminals, respectively, and one of the second and third terminals is output to the first terminal based on the logical value of the second selector signal. Selector (Fig. 1
102), the capacitance (106 in FIG. 1) connected between the connection point of the third terminal of the first selector and the third terminal of the second selector and the ground, and the signal waveform of the output terminal of the selector A differentiating circuit (112 in FIG. 1) for differentiating the buffer output of
And a first and a second selector for the first and second selectors (101 and 102 in FIG. 1) for the output waveform of the differentiating circuit for the waveform input to the input terminal (100 in FIG. 1). When the output waveform of the differentiating circuit (112 in FIG. 1) exceeds the threshold values of the first and second selector signals, the third terminal of the first selector (101 in FIG. 1) is connected to the third terminal. The first and second selectors are switched so that the signal from the input terminal is transmitted to the waveform input unit via the third terminal of the second selector (102 in FIG. 2), thereby preventing overshoot. I do.

In a preferred embodiment of the present invention, a signal input to an input terminal (100 in FIG. 1) is input to a first terminal, and a second and a second signal are input based on a logical value of a third selector signal. A third selector (103) for selectively outputting to one of the three terminals, and a second and third terminal respectively connected to the second and third terminals of the third selector (103 in FIG. 1). A fourth selector (104 in FIG. 1) that outputs one of the second and third terminals to the first terminal based on the logical value of the selector signal of the third selector, and a third terminal and a fourth terminal of the third selector. The capacitance (105 in FIG. 1) connected between the connection point of the third terminal of the selector and the ground, and the inverted output of the signal waveform of the first terminal of the fourth selector in the inverter (110 in FIG. 1). A differentiating circuit (111 in FIG. 1) for differentiating, and an input terminal (100 in FIG. 1) With respect to the input waveform, the output waveform of the differentiating circuit (111 in FIG. 1) is supplied as third and fourth selector signals to the third and fourth selectors (103 and 104 in FIG. 1). When the output waveform of the circuit (111 in FIG. 1) exceeds the threshold values of the third and fourth selector signals, the third terminal of the third selector (103 in FIG. 1) and the fourth selector (FIG. 104), the third and fourth selectors are switched so that the signal from the input terminal is transmitted to the waveform input section via the third terminal, thereby preventing undershoot.

The present invention preferably includes the first to fourth selectors and the first and second differentiating circuits to prevent overshoot and undershoot.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. Referring to FIG. 1, the input terminal 100 is connected to a first terminal.
Connected to the first terminal 101-1 of the selector 101,
The second terminal 101-2 of the first selector 101 is connected to the second terminal 101-2.
Connected to the second terminal 102-2 of the selector 102 of
The third terminal 101-3 of the first selector 101 is connected to the second terminal 101-3.
Terminal of the capacitive component 106 and the second selector 10
2, the first terminal of the second selector 102 is connected to the first terminal 103-1 of the third selector 103, and the second terminal of the third selector 103 is connected to the first terminal 103-1 of the third selector 103. Terminal 103-2 of the fourth selector 104 is connected to the second terminal 104-2 of the fourth selector 104, and the third terminal 103-3 of the third selector 103 is connected to the first terminal 103-1 of the first capacitive component 105.
Terminal and the third terminal 104-3 of the fourth selector 104
It is connected to the.

The first terminal 104 of the fourth selector 104
-1 is commonly connected to the input terminals of the waveform input unit 113 and the buffer circuit 109 and the input terminal of the inverter circuit 110;
The output terminal of the buffer circuit 109 is connected to the input terminal of the second differentiating circuit 112, the output terminal of the second differentiating circuit 112 is connected to one terminal of the second pull-down resistor 108, and the first selector 101 and the selector signal of the second selector 102 (second selection signal).
, And a second pull-down resistor 1
08 is connected to GND.

The output terminal of the inverter circuit 110 is connected to the input terminal of the first differentiating circuit 111 and the first differentiating circuit 11
1 is connected to one terminal of the first pull-down resistor 107, the selector signal of the third selector 103 (third selection signal), and the selector signal of the fourth selector 104 (fourth signal). Selection signal), and the other terminal of the first pull-down resistor 107 is connected to GND.

The second terminal of the first capacitive component 107 and the second terminal of the second capacitive component 108 are both connected to GND.

Here, the gate delays of the first selector 101, the second selector 102, the third selector 103, and the fourth selector 104 are all Ts, and the buffer circuit 1
09, the gate delay of the inverter circuit 110 is Ti, the first and second differentiation circuits 111, 1112 are Ti.
, The threshold value of the selector signal in each of the buffer circuit 109, the inverter circuit 110, and the first to fourth selector circuits is Vt.

At this time, the input terminal 110 is connected to FIG.
It is assumed that a waveform having a large overshoot as shown in FIG.

At this time, the output terminal of the first differentiating circuit 111 is connected to GND by the first pull-down resistor 107 and is in a low state, and the output terminal of the second differentiating circuit 112 is also connected to the second pull-down resistor. Assuming that the signal is connected to GND and is in a low state by the switch 108, the selector signals of the first to fourth selectors 101 to 104 are set to Lo.
w state and the first terminal 10 of the first selector 101
The signal waveform input to 1-1 passes through the second terminal 101-1 in the first selector 101, and the second terminal 102-2 and the first terminal 1 in the second selector 102.
02-3, passes through the first terminal 103-1 and the second terminal 103-2 in the third selector 103,
In the fourth selector 104, the second terminal 104-2
And the first terminal 104-1, and input to the waveform input unit 113, the input terminal of the buffer circuit 109, and the input terminal of the inverter circuit 110 with a waveform as shown in FIG. Referring to FIG. 2B, a delay 4Ts until the waveform rises is a delay time of four stages of selectors 101 to 104.

The waveform output from the output terminal of the buffer circuit 109 is input to the input terminal of the second differentiating circuit 112, and the signal waveform becomes a waveform as shown in FIG. Referring to FIG. 2C, Tb is a value of buffer circuit 109.
Is the delay time.

The waveform output from the output terminal of the inverter circuit 110 is input to the input terminal of the first differentiating circuit 111, and the signal waveform becomes a waveform as shown in FIG. Referring to FIG. 2D, Ti is a delay time of inverter circuit 110.

At this time, the waveform at the output terminal of the first differentiating circuit 111 is as shown in FIG.
This is input as the selector signal of the third selector 103 and the selector signal of the fourth selector 104, but does not exceed the threshold (threshold).
03 and the selection state of the fourth selector 104 do not change.

The waveform at the output terminal of the second differentiating circuit 112 is as shown in FIG. 2F, which is input as the selector signal of the first selector 101 and the selector signal of the second selector 102. However, since the threshold Vt is exceeded, the time Td during which the threshold Vt is exceeded is
In the first selector 101, the selection is changed from the second terminal 101-2 to the third terminal 101-3 by s,
In the second selector 102, the second terminal 102-2
Is changed to the third terminal 102-3.

At this time, the third terminal 101-3 of the first selector 101 and the third terminal 101-3 of the second selector 102 wait until the waveform passed through the first selector 101 is input to the second selector 102. While the third terminal 103-3 is selected, the waveform is rounded by the second capacitive component 106, and a waveform that does not easily generate crosstalk noise is input to the waveform input unit 113.

Similarly, when a falling waveform having a large undershoot is input to the input terminal, a waveform that does not easily generate crosstalk noise is input to the waveform input unit.

In this embodiment, it is needless to say that a clamp diode for removing noise may be provided.

[0024]

As described above, according to the present invention,
A selector for selecting a transmission path of an input signal and adding a capacitive component to the path; a buffer circuit and an inverter circuit having an output of the selector as an input; and a differentiating circuit for differentiating outputs of the buffer circuit and the inverter circuit, respectively. And a selector that switches and selects the selector based on the output of the differentiating circuit, so that a waveform that does not easily generate crosstalk noise is input to the waveform input unit without increasing the delay time. The effect that can be done.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a timing chart of one embodiment of the present invention.

[Explanation of symbols]

 101 first selector 102 second selector 103 third selector 104 fourth selector 105 first capacitive component 106 second capacitive component 107 first pull-down resistor 108 second pull-down resistor 109 buffer circuit 110 Inverter circuit 111 First differentiating circuit 112 Second differentiating circuit 113 Waveform input unit

Claims (4)

(57) [Claims] An input signal from an input terminal to a waveform input section.
As a transmission path, a path to which a capacitive component is added or
And first and second selection means for switching and selecting a non-existing route.
For example, is connected to the first selection means is an input terminal said input terminals
And the second selecting means has an input terminal connected to the first selecting means.
Output terminal, and the output terminal is connected to the waveform input section.
Is provided with a buffer circuit and an inverter circuit for receiving the output of said second selection means in common, the first and second differentiating circuit for differentiating the outputs of the buffer circuit and the inverter circuit, wherein The outputs of the first and second differentiating circuits are respectively
And as a selection signal of the second selection means, for the steep rising and falling input signal waveforms ,
The first selection means and the second selection means use a capacitive component.
An undershoot / overshoot prevention circuit, characterized in that the input signal waveform is dulled and transmitted to the waveform input section by switching and selecting the added path . 2. A first selector for selectively outputting a signal input to an input terminal to one of first and second output terminals based on a value of a first selection signal, and a first selector of the first selector. , A second output terminal to the first, second
, And outputs one of the first and second input terminals to an output terminal based on the value of a second selection signal.
And a first terminal connected between the connection point of the second output terminal of the first selector and the second input terminal of the second selector and ground.
And a first differentiating circuit for differentiating a buffer output of a signal waveform at an output terminal of the second selector. The first and second selection signals are supplied to the first and second selectors from the output waveform, and the output waveform of the first differentiating circuit sets the threshold value of the first and second selection signals. The first and second signals are transmitted such that a signal from the input terminal is transmitted to a waveform input unit via a second output terminal of the first selector and a second input terminal of the second selector when the signal exceeds the threshold. An input circuit in which a second selector is switched to prevent overshoot. 3. A third selector for selectively outputting a signal input to an input terminal to one of first and second output terminals based on a value of a third selection signal, and a first selector of the third selector. , A second output terminal to the first, second
, And outputs one of the first and second input terminals to the output terminal based on the value of the fourth selection signal.
And a second terminal connected between the connection point of the second output terminal of the third selector and the second input terminal of the fourth selector and ground.
And a second differentiating circuit for differentiating the inverted output of the signal waveform at the output terminal of the fourth selector. The second differentiating circuit for the signal input to the input terminal The third and fourth selection signals are supplied to the third and fourth selectors from the output waveform, and the output waveform of the second differentiating circuit sets the threshold value of the third and fourth selection signals. When the signal exceeds the third input terminal, a signal from the input terminal is transmitted to a waveform input unit via a second output terminal of the third selector and a second input terminal of the fourth selector. An input circuit wherein the fourth selector is switched to prevent undershoot. 4. A first selector for selectively outputting a signal input to an input terminal to one of a first output terminal and a second output terminal based on a value of a first selection signal, and a first selector of the first selector. , A second output terminal to the first, second
, And outputs one of the first and second input terminals to an output terminal based on the value of a second selection signal.
And a first terminal connected between the connection point of the second output terminal of the first selector and the second input terminal of the second selector and ground.
A third selector for selectively outputting the output of the second selector to one of first and second output terminals based on a value of a third selection signal; and a first selector of the third selector. The first and second terminals are connected to the second output terminal.
, And outputs one of the first and second input terminals to the output terminal based on the value of the fourth selection signal.
And a second terminal connected between the connection point of the second output terminal of the third selector and the second input terminal of the fourth selector and ground.
A first differentiating circuit for differentiating the buffer output of the signal waveform at the output terminal of the fourth selector; and a second differentiating circuit for differentiating the inverted output of the signal waveform at the output terminal of the fourth selector. And supplying the first and second selection signals to the first and second selectors from the output waveform of the first differentiating circuit with respect to the signal input to the input terminal, The third and fourth selection signals for the third and fourth selectors are supplied from the output waveform of the second differentiating circuit, and the output waveform of the first differentiating circuit is the first and second selecting signals. When the threshold value of the selection signal is exceeded, a signal from the input terminal is output to the second output terminal of the first selector, the second input terminal of the second selector, and the third and fourth terminals. The first and second signals are transmitted to the waveform input unit via the selector.
When the output waveform of the second differentiating circuit exceeds the threshold value of the third and fourth selection signals, the second output terminal of the third selector and the fourth selector are switched. An input circuit, wherein the third and fourth selectors are switched so that a signal from the second selector is transmitted to the waveform input unit via the second input terminal.