JPH01298830A - Data processing transmission equipment - Google Patents

Abstract

PURPOSE:To prevent the effect on other processing circuit even without some processing circuits by providing a bypass circuit giving an input data to or bypassing it through a corresponding processing circuit according to a control signal to an input/output section of each processing circuit. CONSTITUTION:A control signal is given to bypass circuits B1-Bn provided to an input/output section of processing circuits P1-Pn. The transmitter is controlled to bypass an input data through a processing circuit P2 not requiring any signal processing due to missing and to pass the input data through other processing circuits P1, P3-Pn requiring the signal processing. Moreover, in case of bypassing a data by a delay section provided with bypass circuits B1-Bn, a prescribed delay time is given to attain the processing and transmission on the data requiring the timing. Thus, the data processing and transmission are implemented normally independently of the processing circuit.

Description

[Detailed Description of the Invention] [Summary] Regarding a data processing and transmission device that transmits digital data processed by a plurality of processing circuits via a data bus, In order to prevent this from affecting the input data, a bypass circuit is provided at the input/output section of each processing circuit to pass the input data to the corresponding processing circuit according to the control signal, or to bypass the input data from the previous stage. A pair of bypass circuits and an input/output circuit are provided, and the bypass circuit passes or bypasses the manual data from the previous stage to the corresponding input/output circuit according to the control signal, and the input/output circuit passes the manual data from the previous stage to the corresponding input/output circuit according to the control signal. The input data from the input/output circuit or the corresponding bypass circuit is sent to the bypass circuit and the subsequent input/output circuit through the corresponding processing circuit, or all processing circuits and data buses are prepared for current use and for backup. , each processing circuit is configured to select output data from the current processing circuit or preprocessing circuit at the previous stage and send it to each processing section in accordance with the control signal, and send the processed data to the current processing circuit and the preprocessing circuit at the subsequent stage.

(Industrial Application Field) The present invention relates to a data processing and transmission device, and more particularly to a data processing and transmission device that transmits digital data processed by a plurality of processing circuits via a data bus.

In equipment that processes digital data using multiple processing circuits and transmits it over a data bus, processing circuits must be replaced, deleted, or added not only in the event of a processing circuit failure, but also in order to improve equipment functionality or inspect parts of the equipment. It is necessary to do so.

[Conventional technology]

FIG. 17 shows a conventional data processing and transmission device that serially transmits digital data from a plurality of processing circuits via a data bus. In this device, n processing circuits are connected in series via a data bus DB. has been done.

As shown in FIG. 18, each processing circuit in this case connects a processing module PM to the processing stage by providing a flexible flop F/F at the input/output stage (initial stage and final stage).
Processing module P M 1- of each processing circuit P1 to Pn
An arbitrary number of P M n can be connected in series.

The flow of data in such a data processing and transmission device will be explained with reference to FIG.
After signal processing (for example, multiplexing processing) is performed, the signal is returned to the data bus DB, sent to the next stage processing circuit P2, where signal processing (multiplexing processing) is performed, and such processing operations ( The multiplexing processing operation) is performed up to the n-th stage processing circuit Pn and sent out as output data.

[Problem to be solved by the invention]

In such a conventional data processing and transmission device, as shown in FIG. 20, if the processing circuit P2 is disconnected or malfunctions, data transmission will stop in that processing circuit, and the entire device will be damaged. There was a problem that the device would end up in the same state as the failure.

Therefore, the present invention provides a data processing and transmission device that transmits digital data processed by a plurality of processing circuits via a data bus so that even if some processing circuits are missing, other processing circuits are not affected. It is intended to.

[Means to solve the problem]

FIG. 1 is a diagram conceptually showing a data processing and transmission device according to the first invention, which has been made to achieve the above object.
At the input/output section of each of the processing circuits P1 to Pn, bypass circuits Bl to Bn are provided which pass input data through or bypass the corresponding processing circuits P1 to Pn according to a control signal.

In the first aspect of the present invention, each of the bypass circuits B1 to Bn may have a delay section, and the delay section may delay data for a predetermined time when data is bypassed.

FIG. 2 conceptually shows the data processing and transmission device according to the second invention, in which a pair of bypass circuits are provided at the input/output portions of each of the processing circuits P1 to Pn, both of which receive manual data from the previous stage. B1 to Bn and input/output circuits 01 to Cn are provided, and the bypass circuits B1 to Bn pass or bypass the input data from the previous stage to the corresponding input/output circuits C1 to Cn according to control signals, and The circuits C1 to Cn pass the input data from the input/output circuits in the previous stage or the corresponding bypass circuits 81 to Bn to the corresponding processing circuits P1 to Pn according to the control signal, and pass the input data from the input/output circuits in the previous stage or the corresponding bypass circuits 81 to Bn to the input/output circuits in the bypass circuits 81 to Bn and the input/output circuits in the subsequent stage. The data is sent to C1 to Cn.

Also in this second invention, bypass circuits B1-Bn
may each have a delay section 12, and the data passing through the delay section 12 may be delayed by a predetermined time necessary for processing in each processing circuit P1xPn.

Furthermore, FIG. 3 conceptually shows a data processing and transmission device according to the third aspect of the present invention, in which all processing circuits P1 to Pn and a data bus DB are prepared for use and for spare parts, and each processing circuit P
1 to Pn select the output data of the previous stage current processing circuit or preprocessing circuit according to the control signal and send it to each processing section, and also send the processed data to the subsequent stage current processing circuit and preprocessing circuit. .

[For production]

In FIG. 1, control signals are given to bypass circuits B1 to Bn provided at the input/output sections of each processing circuit P1 to Pn, and input data is passed to processing circuit P2 that does not require signal processing due to being removed. Control other processing circuits PI, P that require signal processing to bypass that processing circuit.
3 to Pn are controlled to pass input data.

Further, in the first aspect of the present invention, by providing a delay section in each of the bypass circuits B1 to Bn and giving a predetermined delay time when bypassing data, it is possible to process and transmit data that requires timing.

In this way, data processing and transmission can be performed normally regardless of the presence or absence of a processing circuit.

In the second invention shown in FIG.
During normal operation, as shown by the dotted line, the processing circuits P1 to Pn receive output data from the bypass circuit or input/output circuit, and send the processed data to the corresponding bypass circuit and subsequent input/output circuit. However, when the processing circuit is disconnected or in the event of a failure, the control signal bypasses the processing circuit like the bypass circuit B2 and transfers data to the next bypass circuit B3. Furthermore, when a failure occurs in the bypass circuit B4, the input/output circuit C4 corresponding to the failed bypass circuit B4 selects the output data of the preceding input/output circuit B3 and sends it to the processing circuit P4 for processing. , and sent to the next stage input/output circuit B5 (not shown).

Thereby, even if a failure occurs not only in the processing circuit but also in the bypass circuit, input data can be processed and transmitted.

In this second invention as well, if data is delayed by a predetermined time required for processing in each processing circuit P1 to Pn in the delay section of the bypass circuits 81 to Bn, the same effect as in the first invention can be achieved. It is possible to process and transmit data that requires timing.

Furthermore, in the third aspect of the present invention shown in FIG. 3, during normal operation, data processing and transmission is performed through the current route as shown by the thick line in FIG. When this happens, the spare processing circuit P12 corresponding to the processing circuit P22 is activated by a control signal as shown in FIG. 4(b).
selects and processes the output data from the current processing circuit P21 in the previous stage, and then sends it to the current and preliminary processing circuits P13 and P23 in the subsequent stage.

This allows input data to be processed and processed even in the event of a processing circuit failure.
It can be executed without stopping the transmission.

[Embodiments] Hereinafter, embodiments of the data processing and transmission device according to the present invention will be described.

FIG. 5 shows an embodiment of each bypass circuit Bl-Bn used in the data processing and transmission device of the first invention conceptually shown in FIG. Distribution unit 11 for distribution to both circuits and data buses
, a delay unit 12 that delays data to the data bus by the delay time in the processing circuit, and a selection unit 13 that selects between the delayed data from the delay unit 12 and the data processed by the processing circuit using a control signal. It is made up of.

Incidentally, the distribution section 11 may also use a control signal to select data to be sent to the processing circuit and data to be sent to the data bus, similarly to the selection section 13. Also, the control signal may be sent separately to each of the bypass circuits Bl-Bn. It is a signal that is given (in parallel) to the processor and is generated knowing the processing circuit that has been removed.

Next, the operation of the embodiment shown in FIG. 5 will be explained using FIG. 6.

FIG. 6(a) shows the operation when the processing circuit is connected to the data bus DB, and the distribution section 11 constantly distributes input data to the delay section 12 and the processing circuit. Then, the delay unit 12 delays the human input data by a time (measured in advance) that is predicted to be necessary for the input data to be processed by the processing circuit, and provides the delayed data to the selection unit 13 . Note that this delay section 12 is used only when timing adjustment is required for data processing and transmission, and does not need to be used in other cases. Processed data from the processing circuit is input, and the selection unit 13 selects, in response to a control signal, the data from the processing circuit to be sent to the next processing circuit as output data.

FIG. 6 (5) shows the operation when the processing circuit is not connected to the bypass circuit but is disconnected. In this case, the selection section 13 selects the data from the delay section 2 by the control jn signal. is selected to be sent to the next processing circuit as output data.

FIG. 7 shows an embodiment in which the data processing and transmission device according to the present invention is used on the receiving side to separate data. In this embodiment, high-speed data flows through the data bus DB, and from there the processing circuit In the figure, Bl-Bn is a bypass circuit, and P1 is a circuit for extracting low-speed data at an arbitrary speed.
-Pn are processing circuits each composed of a frequency divider that divides a common input clock at a predetermined ratio, and a flip-flop F/F that takes out data based on the clock output of this frequency divider. Further, control signals to each of the bypass circuits 81 to Bn are generated by switches S W l to S W n.

Next, the operation of this embodiment will be described in the operation explanatory diagram of FIG.
This will be explained with reference to the time chart shown in the figure.

The input data first enters the bypass circuit B1 as shown in Figure 6(a).
As shown in the figure, the distribution section 11 distributes the data to the delay section 12 and the processing circuit P1, and the data delayed by the delay section 12 is sent to the selection section 1.
3 is input. On the other hand, the data sent to the processing circuit PI is input to the flip-flop F/Fl, and as shown in FIG. data l (data frequency l/2 of every other input data
).

The data distributed by the bypass circuit B1 is applied to the flip-flop F/Fl in the processing circuit PI as described above, and returns to the selection section 13 of the bypass circuit B1 again. At this time, the selection section 13 of the bypass circuit B1 is switched to select the data from the processing circuit PI by the control signal generated by the closing of the switch SWl, so the output data of the delay section 12 is not selected. The input data returned from the processing circuit P1 is selected and sent to the bypass circuit B2. Therefore, in this embodiment, bypass circuit B1. The delay section 12 is set so that the delay time of the data from being distributed to the processing circuit PI and returning to the bypass circuit Bl is the same as the delay time given by the delay section 12. However, in the case of this embodiment, the timing of data processing and transmission does not matter, so the delay time can be ignored.

Since no processing circuit is connected to the bypass circuit B2, the switch SW2 is open, and therefore the selection section 13 selects the input data delayed by the delay section 12 and sends it to the next bypass circuit B3.

Flip-flop F/F3 distributed by bypass circuit B3
The input data is passed through the frequency divider D in the processing circuit P3.
Data 3 (data frequency 1/6 of every sixth input data) shown in FIG.

Other points are the same as those of the bypass circuit B1 and the processing circuit PI.

In this way, input data is outputted through n bypass circuits, while separated data at a desired speed is obtained.

In this embodiment, when changing the speed of separated data, the frequency division ratio of the processing circuit is changed, but this processing circuit can be inserted or removed freely by opening the switch, and other processing The circuit can continue to operate during this time.

In the method according to the first invention described above, data always passes through the bypass circuit before and after passing through the processing circuit, so if the bypass circuit breaks down, data transmission will stop at that part, and so on. There is a problem in that the entire device falls into the same state as if it had failed.

Therefore, in the second aspect of the present invention, even if the bypass circuit fails, processing and transmission of the data is made possible by bypassing the data.

For this reason, in the second invention, the input/output circuits C1 to Cn are provided in pairs with the respective bypass circuits B1 to Bn as shown in FIG. is shown in FIG. That is, each input/output circuit is connected to the selection section 2.
1 and a distribution section 22, and the selection section 21 controls the output data from the distribution section 11 of the bypass circuit and the output data from the previous stage input/output circuit (or the input data itself if the input/output circuit is the first stage). The distribution section 22 selects and sends the data to the processing circuit according to the signal, and the distribution section 22 simultaneously sends the data processed by the processing circuit to the selection section 13 of the corresponding bypass circuit and the selection section 21 of the subsequent input/output circuit. It is. The configuration of the bypass circuit is the same as that shown in FIG.

FIG. 10 shows the operation when three bypass circuits and three input/output circuits are used in the embodiment shown in FIG. It shows the flow of data when

First, the data reaches the bypass circuit B1 and the input/output circuit CI. In the bypass circuit Bl, the data is further divided into two by the distribution section 11 and sent to the delay section 12 and the selection section 21 of the input/output circuit CI. In the selection section 21 of the input/output circuit C1, one of the data coming from two directions is selected (this is controlled by a control signal, but in normal operation, no matter which one is selected, it will not change). , which in this embodiment selects input data), is sent to the processing circuit Pi.

The data processed by the processing circuit P1 is divided into two by the distribution section 22 of the input/output circuit CI, one of which is distributed to the subsequent input/output circuit C2.
to the selection section 21 of the bypass circuit B1, and the other to the selection section 13 of the bypass circuit B1.
sent to. The data sent to the bypass circuit Bl passes through the selection section 13 (at this time, the selection section 13 is switched by a control signal as shown in the figure), and is then sent to the bypass circuit B.
It is sent to the distribution unit 11 of No. 2. In this case, the control signal provides a selection signal to the selector SEL so as to select either the output data of the bypass circuit B3 or the input/output circuit C3.

Data transmission and processing is performed in this manner.

Next, FIG. 11 shows the flow of data when the bypass circuit B2 fails. As shown in FIG. 10, data is transmitted in parallel on the data bus between the bypass circuits and between the input and output circuits. Therefore, there is no need for any particular control signal to be used for control, and the data flows through the route of the input/output circuit C2 without interference, allowing data transmission without affecting other parts.

Further, the flow of data when the processing circuit P2 is not installed is shown in FIG. By performing control to switch to the bypass circuit B2, data can be passed to the bypass circuit B2. This allows data transmission without affecting other parts.

FIGS. 13 and 14 show an embodiment in which the data processing and transmitting apparatus according to the second invention is applied to a separation circuit similarly to the first invention shown in FIG.

In FIG. 13, the flow of signals when bypass circuit B2 fails is shown by thick lines, and input data flows around bypass circuit B2, passes through input/output circuits 01 to C3, and becomes output data. . Separation circuit PI-P as a processing circuit
In No. 3, the input clock can be frequency-divided and desired data can be extracted using the F/F. In this way, even if the bypass circuit fails, the isolation operation can be performed without any effect.

FIG. 14 shows the data flow when the separation circuit P2 is not installed. In this case, the data is transferred to the separation circuit P2.
The signal passes through the bypass circuit B2 at the portion shown in FIG. With this, the separation circuits P1 and P3 can extract the desired signals. In this way, the separation operation can be performed without any influence even if the separation circuit is not installed.

Although the control signal is not shown, the selection section in the bypass circuit and the selection section in the input/output circuit are connected to the microcomputer and are given from the microcomputer.

The data processing and transmission device according to the third aspect of the present invention further solves the problem by duplicating the data bus and the processing circuit (current and spare) and detouring the data in the part where the processing circuit has failed to the spare processing circuit. This is what I did.

FIG. 15 shows an embodiment of the processing circuit used in the third aspect of the present invention, in which an input/output circuit consisting of a selection section 31 and a distribution section 32 is arranged together with a processing separation section 33 in a panel of the processing circuit. There is. In this case, the selection unit 31 receives each output data from the current and backup processing circuits in the previous stage (in the case of the first stage, data from the current bus and the backup bus), selects the data based on the control signal, and sends the data to the processing unit 33. The data processed by the processing section 33 is sent to the distribution section 32, divided into two, and sent to the next-stage current and preliminary processing circuits.

An embodiment in which a processing circuit having such an input/output circuit is applied as a separation circuit is shown in FIG.
This is a circuit whose purpose is to extract low-speed data at an arbitrary speed. The part corresponding to the processing circuit here is F/F
It consists of a frequency divider and a frequency divider. In addition, the current processing circuit P21
and preliminary processing circuit P11, current processing circuit P22 and preliminary processing circuit P12, and current processing circuit P23 and preliminary processing circuit P13.
are the same circuit.

In this embodiment, the signal flow when the current processing circuit P22 fails is shown by a thick line. In other words, the human data is
It becomes output data through the current processing circuit P21, preliminary processing circuit P12, and current processing circuit P23. At this time, each processing circuit divides the human clock in the same way as in the above case, and
/F allows the desired data to be retrieved, and even if the current processing circuit P22 fails, the preliminary processing circuit P12 performs the same function, so the desired data can be retrieved.

In this way, even if the processing circuit fails, the target data is output, and separation operations can be performed without any effect.

〔Effect of the invention〕

As described above, according to the data processing and transmission device of the first aspect of the present invention, a bypass circuit is provided at the input/output section of each processing circuit to pass or bypass input data to the corresponding processing circuit according to the control signal. , it is possible to perform predetermined processing on input data regardless of the presence or absence of a processing circuit, the processing circuit can be easily changed even while the device is in operation, and the reliability of the device is improved. Furthermore, in this case, by providing a delay section in the bypass circuit and delaying the bypass data for a predetermined period of time, the present invention can be applied to devices that require timing for data processing and transmission.

Furthermore, in the second invention, even if the bypass circuit fails, it can be bypassed by input/output circuits provided corresponding to each processing circuit, and in the third invention, a spare processing circuit is provided as a bypass circuit. Since data can be detoured, there is no problem with data processing and transmission even if any bypass circuit or processing circuit on the data bus fails, and the reliability of the device is significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a data processing and transmitting device according to the first invention, FIG. 2 is a principle block diagram of a data processing and transmitting device according to the second invention, and FIG. 3 is a principle block diagram of a data processing and transmitting device according to the second invention. A block diagram of the principle of such a data processing and transmission device, FIG. 4 is an explanatory diagram of the operation of the present invention in Section 3@I, FIG. 5 is a block diagram showing an embodiment of the bypass circuit, and FIG. 6 is a diagram illustrating the operation of the bypass circuit. 7 is a block diagram showing an embodiment in which the first invention is applied to a separation circuit, FIG. 8 is a time chart diagram of the embodiment of FIG. 7, and FIG. A block diagram showing an embodiment of the bypass circuit and input/output circuit used in the data processing and transmission device according to the present invention, FIGS. 10 to 12 are diagrams for explaining the operation of the second embodiment of the present invention, 13 and 14 are block diagrams showing an embodiment in which the second invention is applied to a separation circuit, and FIG. 15 is a block diagram showing an embodiment of a processing circuit used in a data processing and transmission device according to the third invention. 16 is a block diagram showing an embodiment in which the third invention is applied to a separation circuit, FIG. 17 is a block diagram showing a conventional data processing transmission device, and FIG. 18 is a block diagram showing a row of processing circuits. 19 and 20 are block diagrams showing the flow of input data in the conventional example. In FIGS. 1 to 3, P1 to Pn...processing circuit, Bl-Bn...bypass circuit, C1 to Cn...input/output circuit, DB...data bus, 12...delay section. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] (1) In a data processing and transmission device that transmits data processed by multiple processing circuits (P1 to Pn) via a data bus (DB), input is input to the input/output section of each processing circuit (P1 to Pn) according to a control signal. A data processing and transmission device characterized in that a bypass circuit (B1 to Bn) is provided for passing data through or bypassing a corresponding processing circuit (P1 to Pn). (2) The bypass circuit (B1 to Bn) is a delay section (12)
2. The data processing and transmission device according to claim 1, further comprising: a delay section (12) for delaying data passing through the delay section (12) by a predetermined time required for processing in each processing circuit (P1 to Pn). (3) In a data processing and transmission device that transmits data processed by a plurality of processing circuits (P1 to Pn) via a data bus (DB), the input and output sections of each processing circuit (P1 to Pn) are connected to each other from the previous stage. A pair of bypass circuits (B1 to Bn) that receive input data
) and input/output circuits (C1 to Cn), and the bypass circuits (B1 to Bn) pass or bypass the input data from the previous stage to the corresponding input/output circuits (C1 to Cn) according to the control signal. The input/output circuits (C1 to Cn) process input data from the preceding stage input/output circuit or the corresponding bypass circuit (B1 to Bn) according to the control signal to the corresponding processing circuit (
A data processing transmission device characterized in that the data is sent to the bypass circuit (B1 to Bn) and subsequent input/output circuits (C1 to Cn) through the input/output circuits (P1 to Pn). (4) The bypass circuit (B1 to Bn) is a delay section (12)
4. The data processing and transmission device according to claim 3, further comprising: a delay section (12) for delaying data passing through the delay section (12) by a predetermined time period required for processing in each processing circuit (P1-Pn). (5) In a data processing and transmission device that transmits data processed by multiple processing circuits (P1 to Pn) via a data bus (DB), all processing circuits (P1 to Pn) and the data bus (DB) are used as current parts. A spare portion is prepared, and each processing circuit (P1 to Pn) selects the output data of the previous stage current processing circuit or preliminary processing circuit according to the control signal and sends it to each processing section, and also sends the processed data to the subsequent stage current processing circuit and backup processing circuit. A data processing transmission device characterized in that the data is sent to a processing circuit.