JPH01300560A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress the deterioration of the switching characteristic of a transistor and the decrease in the current amplification factor of a large current region by forming one conductivity type emitter region and additional region in a reverse conductivity type base region in a collector region. CONSTITUTION:One conductivity type collector region 14 formed on a semiconductor substrate 1, reverse conductivity type base regions 3, 4 formed in the collector region, emitter regions 5, 6 formed selectively in the regions 3, 4, an anode region 7 of the same conductivity type additional diode, and a reverse conductivity type cathode region 8 in the region 7 are provided. Thus, since a stable additional diode is provided between the base and the emitter of a power transistor, the current amplification factor of a large current and switching characteristic of the essential characteristics of the transistor are not resultantly deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of a semiconductor device and its manufacturing method, and more particularly to a high-speed switching power transistor.

Conventional technology Conventionally, in order to improve the switching characteristics of high-speed switching transistors, the resistance of the high-resistance region of a single-crystal wafer used as a semiconductor substrate has been lowered or the thickness of the high-resistance region has been thinned. However, with the manufacturing method described above, not only was it not possible to significantly improve the switching characteristics, but it was also difficult to increase the breakdown voltage, which is one of the main electrical characteristics of a transistor. In order to eliminate these drawbacks, a diode is formed between the base and emitter of the transistor to quickly remove minority carriers such as electrons and holes injected into the device.
Efforts have been made to reduce absorption, shorten the lifetime (and shorten the switching characteristics of transistors. For example, in the high-speed switching Darlington transistor, a diode is placed between the base region and emitter region of the drive stage transistor. For example, as shown in the cross-sectional view of FIG. 4, an npn-type Darlington transistor with this structure uses a silicon dioxide film 2 covering the upper surface of a semiconductor substrate 1 with an NN structure as a mask. Through the selective diffusion process, the P-type base regions 3, 4
and N-type emitter regions 5, 6 and anode regions 7 and P
A mold cathode region 8 is formed, and a base electrode 9 is formed.
An electrode lO and an emitter electrode 11 connecting the emitter region 5 of the drive stage transistor and the base region 4 and cathode region 8 of the output stage transistor are formed as shown, and a collector electrode 12 is also formed. Note that 13 is a channel blocking area.

FIG. 5 is an equivalent circuit of an npn type Darlington transistor having such a structure, in which the n type anode region 7 and the P
The circuit structure is such that a diode Di provided in the type cathode region 8 is connected between the base and emitter of the drive stage transistor.

Problems to be Solved by the Invention However, in the structure shown in FIG. 4, the base electrode 9. Connection of drive stage transistor and output stage transistor and additional region diode electrode 10. When the emitter electrode 11 is formed, an alloy layer 15 of silicon and aluminum is formed as shown in the cross-sectional diagram of the additional diode region in FIG. When the diffusion depth of the cathode region 8 of the additional diode is shallow, the depth of the alloy layer 15 of silicon and aluminum is deeper than the cathode region 8 (and it no longer has the effect as a diode. If an alloy layer is not formed, the contact resistance will increase, resulting in a decrease in the current amplification factor for large currents, which are the main characteristics of power transistors, and a thick collector and resistance.

The present invention provides an optimum value for the diffusion length of the opposite conductivity type region formed in the additional region in order to suppress the deterioration of the switching characteristics of the transistor and the decrease in the current amplification factor in the large current region.

Means for Solving the Problems To achieve this object, the present invention provides a collector region of one conductivity type formed on a semiconductor substrate, a base region of the opposite conductivity type in the collector region, and a base region of the opposite conductivity type in the base region. An emitter region and an anode region of an additional diode of the same conductivity type are selectively formed, and a cathode region of an opposite conductivity type is provided in the anode region, and the diffusion depth of the cathode region is formed to be 2.0 μm or more. This is a featured semiconductor device and its manufacturing method.

According to the present invention, a power transistor is provided with a stable additional diode between the base and emitter of a power transistor, and as a result, the main characteristics of a power transistor, such as current amplification factor and switching characteristics for large currents, are not deteriorated. It provides:

EXAMPLE An example of the present invention will be described below with reference to the drawings. For example, in the case of a high-speed switching Darlington transistor, FIG. 1 shows a process flowchart of an npn type transistor in which a diode is built between the base and emitter of a drive stage transistor.

First, as shown in Figure 1(a), the thickness of the phosphorus-added layer is 280 mm.
A .mu.m N-type semiconductor substrate 1 (90 .OMEGA.cm.sup.2) is oxidized to form a silicon dioxide film. Thereafter, after removing the silicon dioxide film on one side, phosphorus is diffused on that surface to form a highly concentrated (N+) collector region 14 with a surface concentration of I x 10''c+a-3 and a diffusion depth of 180 μm.Next. To,
The silicon dioxide film formed on the surface opposite to the collector region 14 is opened by a well-known photolithography technique, and boron, which is a P-type impurity, is diffused and introduced through this opening, as shown in FIG. 1(b). , surface concentration 5×IQI
IIc11-3. Base region 3°4 with diffusion depth 20μm
form. Thereafter, an emitter region and an additional region are formed in the silicon dioxide film on the base region by using the photolithography technique again. Through this opening, as shown in FIG.
1020 equipment-3, emitter region 5 with a diffusion depth of 10 μm,
6 and an additional region 7 are formed. Next, the silicon dioxide film on the additional region is selectively opened and boron, which is a P-type impurity, is diffused to a surface concentration of 5× as shown in FIG. 1(d).
1020cl! 1-3 cathode regions 8 are formed. In this example, the diffusion depth of the cathode region is 2.0 μm,
4.0 μm.

The diffusion time was arbitrarily selected so that the thickness was 6.0 μm. On the semiconductor substrate where the diffusion process has been completed as described above,
After opening the base electrode region, the emitter electrode region, and the electrode region connecting the emitter region of the drive stage transistor and the base region and cathode region of the output stage transistor, as shown in FIG. 9 and an emitter electrode 11 and an electrode 10 connecting the emitter region of the drive stage transistor and the base region and cathode region of the output stage transistor were formed, and a collector electrode 12 which could be bonded to the high concentration collector region on the back side was also formed. . FIG. 2 is a cross-sectional view of the main diode region of a typical device according to the present invention. By providing a deep diffusion depth in the cathode region 8 with respect to the alloy layer I5 of the electrode material and silicon in the cathode region, it is possible to provide a power transistor that does not impair switching characteristics and main electrical characteristics. .

FIG. 3 shows a comparison of characteristics between the transistor configured as described above and a conventional transistor having a cathode region of 0.5 μm and 1.5 μm. Figure 3 (a) shows the hFE characteristic distribution in the small current region, and Figure 3 (b) shows the DC current amplification factor,
(C) shows the switching characteristics.

Furthermore, when a diode is formed as an additional region between the emitter and the base of the power transistor shown in this example as shown in FIG. 3(d), the diffusion depth of the cathode region, the switching characteristics (tf), and the current rating (Ic) The relationship between the collector current value when the peak value of the DC current amplification factor is reduced by half is shown. Both the switching characteristics and the collector current rating are in the good range when the diffusion depth is 2.0 μm or more. From the above, if the optimal diffusion depth of the opposite conductivity type region formed in the -conductivity type additional region is selected to be 2.0 μm or more, a transistor without deterioration in switching characteristics and current amplification factor can be realized. As is clear from the figure, according to this example, the variation in hFE at a small current is reduced,
A transistor that does not deteriorate the DC current amplification factor or switching characteristics can be provided.

Although the above embodiments relate to npn darlington transistors, it goes without saying that the same effect can be obtained in transistors in which an additional region is formed between the base and emitter, such as pnp darlington transistors and single transistors.

Effects of the Invention According to the semiconductor device and its manufacturing method of the present invention described above, the variation in hFE at a small current is reduced compared to the conventional method, and the transistor is produced without deteriorating the current amplification factor or switching characteristics. can be provided.

[Brief explanation of the drawing]

1(a) to (e) are step-by-step sectional views showing the manufacturing process of a transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of the main diode region of a transistor according to an embodiment of the present invention, and FIG. 3(a)
- (d) are characteristic diagrams comparing the characteristics of the device according to the present invention with those of the conventional device, and Figs. be. 1...N-type silicon, 2...Silicon dioxide film, 3...Drive stage (transistor) base region, 4...Output stage (transistor) base Region, 5... Drive stage emitter region, 6...
...Output stage emitter region, 7...Additional region, 8
... Cathode region, 9 ... Base electrode, 10 ... Drive stage and output stage connection electrode, 11 ...
...Emitter electrode, 12...Collector electrode, 13...Channel stopper, 14...
. . . High concentration collector region, 15 . . . An alloy layer of silicon and electrode material in the cathode region. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 2 Figure 3 Figure I ((A) m=1'-T' Honkanzo 4 running seconds Figure 3

Claims (2)

[Claims] (1) A collector region of one conductivity type formed on a semiconductor substrate, a base region of the opposite conductivity type formed in the collector region, an emitter region and an additional region of one conductivity type formed in the base region. Equipped with semiconductor devices. (2) In the base region within the collector region on the semiconductor substrate,
A semiconductor characterized in that a deep additional region of the same conductivity type as the emitter region is formed together with the emitter region, and a second region having a diffusion depth of an opposite conductivity type region of 2.0 μm or more is formed within the additional region. Method of manufacturing the device.