JP3356523B2 - Transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor.
More specifically, the present invention relates to a power transistor capable of performing a high-speed switching operation.

[0002]

2. Description of the Related Art Conventionally, a power bipolar transistor which handles a large amount of power has been required to have a high withstand voltage, a large current, and an expanded safe operation area (SOA). Therefore, in general, the resistance is increased by increasing the specific resistance and the thickness of the collector layer, and a large chip for widening the active region is performed. However, this increase in resistance results in an increase in the average life until the carrier is eliminated by recombination, that is, the so-called lifetime. As the life expectancy of carriers increases,
Since this becomes a factor that hinders the high-speed operation of the transistor, realizing a high breakdown voltage and a large current of the power bipolar transistor and realizing a high-speed switching characteristic are in conflict with each other.

In order to shorten the life of carriers and obtain high-speed switching characteristics, a method of diffusing heavy metals as a lifetime killer has been used. However, in this method, the heavy metal, which is a lifetime killer, diffuses to an unnecessary area, so that the reverse leakage current, which is fatal to the transistor, increases and the current amplification factor (h _FE ) decreases. Occurs. In addition, the method of performing heavy metal diffusion and particle beam irradiation as a lifetime killer is difficult to control in terms of process and has poor reproducibility. Moreover, there is a limit to shortening the lifetime. Therefore, the storage time (the time from the saturation state where the excess carriers are stored in the base and collector regions to the time when the excess carriers are released and returned to the active region), which is important as the switching-off characteristics of the transistor, is necessarily shorter than a certain limit. Can not do.

Therefore, for example, Japanese Patent Application Laid-Open No.
No. 65, page 2, lower left column, lines 2 to 7 and FIGS. 1 and 2 propose a bipolar transistor which can control the storage time well without the drawbacks of introducing a lifetime killer. Have been. As shown in FIG. 4, this bipolar transistor is formed by connecting a buried base layer 14 over a collector layer 12 and a collector epitaxial layer 13 on a semiconductor substrate 11 to a base layer 15. In such a bipolar transistor provided with the buried base layer 14,
Carriers injected from the emitter 16 easily recombine in the buried base layer 14, and the carrier lifetime can be shortened. Also, paying attention to the carriers injected into the collector, when the transistor is switched from the on state to the off state, the carriers are absorbed and recombined by the reverse base current flowing through the low resistance buried base layer 14. In this transistor, carriers are absorbed through the buried base layer 14 having a low resistance, so that the storage time can be shortened as compared with the conventional one.

[0005]

SUMMARY OF THE INVENTION In a bipolar transistor in which a buried base layer is formed over the collector layer and the collector epitaxial layer, and the buried base layer is connected to the base layer, the buried base layer is formed by the same conductive semiconductor layer. Due to the connection with the layer, the resistance is large, the carrier movement of the collector layer is slow, and the base region having a large resistance hangs from the base electrode as a series resistance. Therefore, even if the buried base layer is formed with a low resistance, the high resistance of the base layer affects the absorption of carriers, and the recombination speed is not sufficiently improved.

[0006] The present invention has been made in order to solve the above problems, providing a faster, tiger <br/> Njisu data structures particularly it is possible to shorten the time to reach the cut-off state from the saturation state of the switching operation The purpose is to do.

[0007]

[0008]

According to the present invention, there is provided a transistor comprising: a first conductivity type collector region provided on a semiconductor substrate; a second conductivity type base region provided in the collector region; And a buried region of a second conductivity type embedded in the collector region, wherein the emitter region, the base region, and the collector region are vertically stacked. A buried region is formed in the collector region of the portion to be laminated, and the buried region is led to a surface of the semiconductor substrate through a high-concentration impurity region; the in Rukoto are connected by wire to the base region
Between the collector and the base.
It has a structure in which a diode is connected .

Here, the first conductivity type and the second conductivity type are:
When one of n-type and p-type is set to the first conductivity type, it means that the other p-type or n-type is the second conductivity type.

The base region is formed so that its periphery is thicker from the surface of the semiconductor substrate to the depth, and the lower part of the emitter region at the center of the base region is formed shallower than the periphery from the surface. The U-shape is formed, and the buried region is formed inside the U-shape, so that the buried region can be formed near the base region, and the carrier in the collector region is recombined in a short time. It is preferable because it can be performed.

[0011]

According to the transistor of the present invention, the carrier absorbing diode is connected between the base and the collector of the transistor in the same direction as the pn junction between the base and the collector. In that case, the carrier remaining in the collector is recombined by the carrier absorbing diode. In this case, the end of the diode connected to the base of the transistor is guided to the surface of the semiconductor substrate in a low-resistance region without passing through the base region, and is directly connected to the base electrode by wiring.
Does not pass through the high resistance base region. As a result, the resistance is very small and the carrier can be absorbed in a short time.

Further, a buried region of the same conductivity type as the base region is formed in the collector region as a semiconductor structure, and the buried region and the base region are connected by wiring, so that a carrier is provided between the buried region and the collector region. Since the absorption diode is formed and the buried region is formed in the collector region near the base region, the moving distance of the carrier is short,
Since the recombination time is short, the switching operation of the transistor can be accelerated, and as a result, the turn-off time from the saturation state to the cutoff state is shortened, the power loss on the electric circuit during this time is reduced, heat generation is reduced, and the heat dissipation device is reduced. Reduce the need for

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a transistor according to the present invention will be described with reference to the drawings. FIG. 1 is a partial cross-sectional perspective view showing the structure of an npn-type transistor which is an embodiment of the transistor of the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIG. 3 is an explanatory diagram showing a manufacturing process thereof.

[0014] In FIG. 1, is epitaxially grown on the semiconductor substrate, for example, n ^- -type are formed by a diffusion in the collector region 1 and the collector region 1 of the first conductivity type of, for example, the second p-type conductivity Base region 2 which is
And an emitter region 3 of, for example, n ⁺ type first conductivity type, formed in the base region 2 by diffusion or the like, a buried region 4 of, for example, p ⁺ type second conductivity type, and the buried region. 4 and a diffusion region 4a of a high-concentration impurity which is conducted to the surface of a ^{p.sup. +} Type semiconductor layer of the same conductivity type. As shown in FIG. 1, the base region 2 is formed so that its periphery is deep toward the inside of the semiconductor layer, its thickness is large, and the center portion below the emitter region is formed shallow from the surface to be a thin layer. The shape is U-shaped. The buried region 4 penetrates through the collector region 1 in the U-shaped concave portion of the base region 2 and, when the base region 2 is removed, is connected to the p ⁺ -type diffusion region 4a communicating with the surface of the semiconductor layer. I have. And an insulating film (not shown) on the surface of the semiconductor layer.
And is connected to the base electrode by a wiring provided through.

That is, in the transistor according to the present invention, the layer of the base region 2 under the emitter region 3 is formed thin,
A buried region 4 having a high impurity concentration is provided in the collector region 1 below the thin base region 2, and the buried region 4 is not directly connected to the base region 2 but is a diffusion region 4a having a high impurity concentration. And is connected to the base electrode via Therefore, the carriers remaining in the collector region are easily captured by the low-resistance buried region 4, escape to the base electrode via the low-resistance diffusion region 4a, and the residual carriers disappear immediately. As a result, the switching speed can be increased, and the turn-off time (t _off ) from the saturation state to the cutoff state can be extremely reduced. The buried region 4 is formed in the collector region 1 with a conductivity type different from that of the collector region 1, and one end of the buried region 4 is connected to the base electrode by wiring on the surface of the semiconductor layer. Thus, the structure is such that a pn junction carrier absorption diode in the same direction as the pn junction is connected between the collector and the base. FIG. 1 shows the collector region 1
Although the electrodes of emitter region 3 are not shown, for example, a collector electrode is formed of gold or the like on the back surface of semiconductor substrate 1a, and an emitter electrode of emitter region 3 is similarly formed of aluminum or the like.

Next, a method of manufacturing the transistor of the present invention is shown in FIG.
This will be described based on the process chart shown in FIG.

First, an n ⁻ -type epitaxial layer 1b is grown on a semiconductor substrate 1a by epitaxial growth.
A part of the collector region 1 is formed (see FIG. 3A).
Next, a p-type base region 2 is formed in the epitaxial growth layer 1b.
The base ends 2a and 2b and the buried region 4 of the diode 5 are formed by ion implantation or diffusion (FIG. 3).
(B)).

Then, epitaxial growth is performed on the base end 2a, 2b and the surface on which the buried region 4 is formed to grow the n ⁻ -type epitaxial layer 1c to form the collector region 1 (see FIG. 3 (c)). Since the temperature becomes high during this epitaxial growth, the impurities at the base ends 2a, 2b and the buried region 4 diffuse into the growing epitaxial layer 1c and spread slightly upward.

After that, a p-type impurity is introduced from the surface of the epitaxial layer 1c to form a base end connected to the base ends 2a and 2b, the base region 2 therebetween, and the buried region 4 adjacent to the base region 2. Is formed (see FIG. 3D).

The base region 2 is made of, for example, a p-type impurity at the end of the base region 2 at the base ends 2a and 2b.
Is formed so deep as to connect with the base ends 2a and 2b, and the central portion therebetween is formed so as to be shallow so as not to connect with the buried region 4, as shown in FIG. , The cross section is formed in a U-shape. This shallow portion has a depth of, for example, about 5 to 50 μm,
The depth is about 5 to 150 μm. As described above, in order to form a deep (thick) impurity region at the end and a shallow (thin) impurity region therebetween, the diffusion step is divided into two steps to introduce impurities separately into the end and the center. Alternatively, impurities having different diffusion speeds, for example, aluminum (Al) and boron (B) are used, and aluminum having a high diffusion speed is adhered to an end portion, and boron having a low diffusion speed is adhered to a center portion, and 1000 to 1380. By diffusing at about ° C, aluminum with a high diffusion speed in the same diffusion time diffuses deeply, and the base region 2 as shown in FIG. 3D can be formed. In the case where impurities are introduced by ion implantation, the depth of the impurity region can be adjusted by adjusting the energy of ion implantation.
Further, the diffusion region 4 a connected to the buried region 4 is formed to be deep similarly to the end of the base region 2 and connected to the buried region 4. In this case, forming the impurity concentration of the diffusion region 4a to be higher than the impurity concentration of the base region 2 is effective for eliminating the residual carriers in a short time as described above.

Further, an impurity such as phosphorus is introduced into a thin central portion of the base region 2 to form an n ⁺ -type emitter region 3 (see FIG. 3E). Although not shown, a contact hole is formed in an insulating film provided on the surface of the semiconductor layer, electrodes are provided in each region, wiring of each electrode is performed, and the buried region 4 is formed in the same manner as in a normal method. The connected diffusion region 4a is connected to the base electrode by wiring.

FIG. 3 shows an equivalent circuit of a transistor according to the present invention, in which a carrier absorption speed-up diode 5 is connected between a collector and a base in the same direction as the pn junction.

In the above, the present invention has been described by taking an npn transistor as an example.
It goes without saying that the same applies to the np transistor. Also, the shapes of the base region and the diode portion are not limited to the examples described above.

[0024]

As described above, according to the present invention, since one end of the diode is connected to the base electrode by wiring between the collector and the base, the minority carriers injected into the collector region are short during switching. In time, it flows through this diode to the base side and is recombined. as a result,
The switching operation can be performed at high speed, and the time required to switch from the saturated state to the cutoff state is reduced. Therefore, power consumption of the electric circuit generated during the switching time is reduced, heat generation can be suppressed, and characteristics such as an amplification factor of a transistor can be improved and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional perspective view showing one embodiment of a transistor of the present invention.

FIG. 2 is an equivalent circuit diagram of the transistor of the present invention.

FIG. 3 is a process cross-sectional view illustrating an example of a method for manufacturing a transistor of the present invention.

FIG. 4 is a cross-sectional view illustrating an example of a conventional transistor.

[Explanation of symbols]

 Reference Signs List 1 collector region 2 base region 3 emitter region 4 buried region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 21/8222 H01L 27/06 H01L 29/737

Claims (2)

(57) [Claims] 1. A collector region of a first conductivity type provided on a semiconductor substrate, a base region of a second conductivity type provided in the collector region, and an emitter of a first conductivity type provided in the base region. And a buried region of the second conductivity type buried in the collector region, wherein the emitter region,
The base region and the collector region are formed so as to have a portion that is vertically stacked, the buried region is formed in the collector region of the stacked portion, and the buried region is formed through a high-concentration impurity region. Guided to the surface of the semiconductor substrate,
The Rukoto are connected by wire to the base region in the semiconductor substrate surface, a carrier absorption between the collector and the base
A transistor to which a speed-up diode is connected . 2. The base region is formed so that its periphery is thicker from the surface of the semiconductor substrate to a depth thereof, and a portion below the emitter region at the center of the base region is formed shallower than the periphery from the surface. the cross-sectional shape is a U-shape, the transistor according to claim 1, wherein formed by the buried region is formed inside the該Ko shape.