JP2006040929A - Semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element in which a heavy metal is diffused in the specific region of a thickness direction and to provide a method of manufacturing the same. <P>SOLUTION: A p-type semiconductor region 12 is formed on one main surface of an n-type semiconductor substrate 51. An Au film is formed on one main surface of the n-type semiconductor substrate 51, and Au is diffused in the n-type semiconductor substrate 51 by a heat treatment. A second n-type semiconductor region 22 is formed on one main surface of an n<SP>+</SP>-type semiconductor substrate 52. Next, the other main surface of the n-type semiconductor substrate 51 and a second n-type semiconductor region 22 are superposed, and fixed by the heat treatment. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a lifetime killer is diffused and a method for manufacturing the same.

  In order to improve the switching characteristics of semiconductor elements such as diodes and transistors, there is a technique for diffusing heavy metals such as gold and platinum into a silicon semiconductor substrate as a lifetime killer. The lifetime killer is a mechanism in which heavy metal atoms diffused in a semiconductor substrate function as a trap and promote the recombination of minority carriers to shorten the minority carrier lifetime.

  However, since heavy metals increase the on-resistance of semiconductor devices, the technique of diffusing the lifetime killer into the semiconductor substrate has a problem that the forward voltage increases although the switching characteristics are improved.

  In order not to increase the forward voltage of the semiconductor device, it is preferable to diffuse heavy metal only in the vicinity of the PN junction. However, the heavy metal has a very large diffusion coefficient in the silicon semiconductor, and is diffused in the entire thickness direction of the semiconductor substrate by normal thermal diffusion. Therefore, there is a problem that heavy metals cannot be distributed only in the vicinity of the PN junction.

Therefore, electron beam irradiation is performed on a semiconductor substrate in which heavy metal is diffused, and defects are uniformly generated almost in the entire thickness direction of the semiconductor substrate, and then lamp annealing is performed, thereby reducing the lifetime of minority carriers. A method of arbitrarily controlling in the thickness direction has been developed (for example, Patent Document 1).
JP 7-226405 A

  However, the technique disclosed in Patent Document 1 has a problem that a complicated manufacturing apparatus is required because it is necessary to cool the surface of the semiconductor substrate opposite to the surface on which lamp annealing is performed. In addition, there is a problem that it is difficult to control temperature and time during lamp annealing and cooling.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor element in which heavy metals are distributed in a specific region in the thickness direction of a semiconductor substrate, and a method for manufacturing the same.

A method for manufacturing a semiconductor device according to a first aspect of the present invention includes:
Forming a second conductivity type second semiconductor region on a surface region of one main surface of the first conductivity type first semiconductor substrate;
Diffusing heavy metal into the first semiconductor substrate;
Fixing a first conductive type second semiconductor substrate in which heavy metal is diffused at a lower concentration than in the first semiconductor substrate, or in which heavy metal is not diffused, to the other main surface of the first semiconductor substrate; It is characterized by providing.

  The other main surface of the first semiconductor substrate may be cut after the step of diffusing heavy metal.

  The second semiconductor substrate may include a third semiconductor region and a fourth semiconductor region fixed to the first semiconductor region of the first semiconductor substrate.

The impurity concentration of the first semiconductor substrate and the fourth semiconductor region of the second semiconductor substrate may be formed to be 1 × 10 ¹⁸ cm ⁻³ or less.

The semiconductor element according to the second aspect of the present invention is:
A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type formed in a surface region of one main surface of the first semiconductor region;
A third semiconductor region of a first conductivity type formed adjacent to the other main surface of the first semiconductor region;
A first electrode electrically connected to the second semiconductor region;
A semiconductor element comprising a second electrode electrically connected to the third semiconductor region,
Heavy metal is diffused in the first semiconductor region and the second semiconductor region, and heavy metal is diffused in the third semiconductor region at a lower concentration than in the first semiconductor region and the second semiconductor region, Alternatively, heavy metals are not diffused.

  A fourth semiconductor region may be provided between the other main surface of the first semiconductor region and the third semiconductor region.

The impurity concentration of the first semiconductor region and the fourth semiconductor region may be 1 × 10 ¹⁸ cm ⁻³ or less.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor element which distributed heavy metal to the specific area | region of the thickness direction of a semiconductor substrate, and its manufacturing method can be provided.

  A semiconductor element according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a diode will be particularly described as an example.

A diode 1 according to the present embodiment is shown in FIG.
The diode 1 includes a first N-type semiconductor region 11, a P-type semiconductor region 12, an N ⁺ -type semiconductor region 21, a second N-type semiconductor region 22, an anode electrode 31, and a cathode electrode 32.

The first N-type semiconductor region 11 (first semiconductor region) is an N-type semiconductor in which an N-type impurity such as phosphorus or arsenic is diffused. The N-type impurity concentration of the first N-type semiconductor region 11 is preferably 1 × 10 ¹⁸ cm ⁻³ or less, and is formed at 1 × 10 ¹⁵ cm ⁻³ in this embodiment. In the first N-type semiconductor region 11, heavy metals such as gold (Au) and platinum (Pt) are diffused throughout the thickness direction.
Further, the thickness of the first N-type semiconductor region 11 is set from the switching characteristics and operating voltage required for the diode 1 as described later, and is formed to 20 μm in the present embodiment.

Here, the reason why the N-type impurity concentration of the first N-type semiconductor region 11 is preferably 1 × 10 ¹⁸ cm ⁻³ or less is based on the following reason.
When the N-type impurity concentration of the first N-type semiconductor region 11 is set low, the breakdown voltage of the diode 1 is increased, but the operating voltage is increased. On the other hand, when the N-type impurity concentration is set high, the operating voltage decreases, but the breakdown voltage of the diode 1 decreases.

However, when the N-type impurity concentration of the first N-type semiconductor region 11 is higher than 1 × 10 ¹⁶ cm ⁻³ , particularly higher than 1 × 10 ¹⁸ cm ⁻³ , the voltage drop in the thickness direction causes heavy metal diffusion. Regardless of whether or not, it tends to be relatively low.
Therefore, when the N-type impurity concentration of the first N-type semiconductor region 11 is formed to be higher than 1 × 10 ¹⁶ cm ⁻³ , particularly 1 × 10 ¹⁸ cm ⁻³ , only in a specific region as in the present embodiment. The diode 1 in which a heavy metal such as gold is diffused and the diode 1 in which a heavy metal such as gold is diffused throughout the diode have relatively close operating voltages and recovery characteristics.
Therefore, in order to obtain the effect of diffusing heavy metal only in a specific region, it is preferable to set the N-type impurity concentration to 1 × 10 ¹⁸ cm ⁻³ or less, and in this embodiment, 1 × It is formed at 10 ¹⁵ cm ⁻³ .

The P-type semiconductor region 12 (second semiconductor region) is a P-type semiconductor in which a P-type impurity such as boron is diffused. The P-type semiconductor region 12 is formed on the surface region of one main surface (upper surface) of the first N-type semiconductor region 11, and the anode electrode 31 is formed on the upper surface of the P-type semiconductor region 12. In the present embodiment, the P-type impurity concentration of the P-type semiconductor region 12 is 5 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ so that the low resistance contact with the interface of the anode electrode 31 can be satisfactorily ^achieved . The thickness is preferably 5 to 20 μm. In the present embodiment, the impurity concentration of the P-type semiconductor region 12 is 1 × 10 ¹⁸ cm ⁻³ and the thickness is 10 μm.
In the P-type semiconductor region 12, like the first N-type semiconductor region 11, heavy metals such as gold and platinum are diffused throughout the thickness direction.

The N ⁺ type semiconductor region 21 (third semiconductor region) is an N type semiconductor in which an N type impurity such as phosphorus or arsenic is diffused, and is formed adjacent to the second N type semiconductor region 22. A cathode electrode 32 is formed on the lower surface of the N ⁺ type semiconductor region 21.
The N type impurity concentration of the N ⁺ type semiconductor region 21 is preferably 1 × 10 ¹⁸ cm ⁻³ or more so that good low resistance contact with the interface of the cathode electrode 32 can be obtained. It is formed to 1 × 10 ²⁰ cm ⁻³ .
The thickness of the N ⁺ type semiconductor region 21 is, for example, 300 μm so as to function well as a support substrate for the first N type semiconductor region 11, the P type semiconductor region 12, and the second N type semiconductor region 22. Has been.

The second N-type semiconductor region 22 (fourth semiconductor region) is an N-type semiconductor in which an N-type impurity such as phosphorus or arsenic is diffused, and is adjacent to the other main surface (lower surface) of the first N-type semiconductor region 11. Is formed.
The N-type impurity concentration of the second N-type semiconductor region 22 is lower than the impurity concentration of the N ⁺ -type semiconductor region 21, and the effect of diffusing heavy metal only in a specific region of the diode 1 is good as in the first N-type semiconductor region 11. Therefore, in this embodiment, it is formed to 1 × 10 ¹⁶ cm ⁻³ .
The thickness of the second N-type semiconductor region 22 is 10 μm for the reason described below in relation to the first N-type semiconductor region 11.

Heavy metal such as gold diffused in the N-type semiconductor region 11 traps minority carriers, so that recombination of minority carriers is favorably promoted and the lifetime of minority carriers is shortened, that is, the recovery time of the diode 1 is reduced. Shorter. However, the forward voltage of the diode 1 increases.
Therefore, assuming that the thickness of the region including the thickness of the first N-type semiconductor region 11 and the thickness of the second N-type semiconductor region 22 is constant, the thickness of the first N-type semiconductor region 11 is the same as that of the second N-type semiconductor region 22. In comparison, when it is relatively increased, the recovery time of the diode 1 is shortened, but the operating voltage is increased. On the other hand, when the thickness of the first N-type semiconductor region 11 is relatively decreased, the operating voltage of the diode 1 is decreased, but the recovery time is increased.

Therefore, the thickness of the first N-type semiconductor region 11 is changed according to the recovery time (switching characteristics) required for the diode 1 and the operating voltage.
In the present embodiment, the first N-type semiconductor region 11 is formed to 20 μm and the second N-type semiconductor region 22 is formed to 10 μm so that a relatively good recovery time can be obtained while lowering the operating voltage of the diode. .
Even if the operating voltage is high, the thickness of the N-type semiconductor substrate 11 can be relatively increased as compared with the present embodiment when the recovery time is important.

The anode 31 is composed of a metal multilayer film made of gold-zinc alloy (Au-Zn), gold-beryllium-chromium alloy (Au-Be-Cr), gold (Au), or the like, and is a P-type semiconductor region. 12 is formed on the upper surface.
The cathode electrode 32 is gold - germanium alloy (Au-Ge) film, or, Au-Ge, nickel (Ni), is composed of a composed multi-layered metal film such as gold (Au), the ^{N +} -type semiconductor region 21 It is formed on the lower surface.

  By adopting the above configuration, Au diffused in the first N-type semiconductor region 11 and the P-type semiconductor region 12 functions as a trap for promoting recombination of minority carriers, and shortens the lifetime of minority carriers. Good switching characteristics. Au increases the forward voltage of the diode 1, but in this embodiment, Au is diffused only in the first N-type semiconductor region 11 and the P-type semiconductor region 12, so that the operating voltage of the diode 1 increases. Can be prevented.

In the above-described embodiment, the N ⁺ type semiconductor region 21 and the second N type semiconductor region 22 have been described as adopting a configuration in which, for example, heavy metal such as gold is not diffused. It is also possible to adopt a configuration in which heavy metal is diffused at a lower concentration than the semiconductor region 11.

Moreover, it is possible to adopt a configuration in which the N ⁺ type semiconductor region 21 and the second N type semiconductor region 22 in the above-described embodiment are formed from one N type semiconductor region. In this case, the N-type semiconductor region may employ either a configuration in which heavy metal is diffused at a lower concentration than the first N-type semiconductor region 11 or a configuration in which heavy metal is not diffused.

  Next, a method for manufacturing the diode 1 according to the embodiment of the present invention will be described with reference to the drawings. The following is an example, and the present invention is not limited to this as long as a similar result can be obtained.

The manufacturing method of the diode 1 according to the embodiment of the present invention includes a step of manufacturing a first semiconductor substrate formed of a first N-type semiconductor region 11 and a P-type semiconductor region 12, and an N ⁺ -type semiconductor region 21. , A process of manufacturing a second semiconductor substrate formed from the second N-type semiconductor region 22, and a process of fixing the first semiconductor substrate and the second semiconductor substrate to complete the diode 1.

A process for manufacturing the first semiconductor substrate will be described with reference to FIGS.
First, as shown in FIG. 2A, an N-type semiconductor substrate 51 is prepared. The N-type semiconductor substrate 51 is a first conductivity type, for example, an N-type semiconductor in which an N-type impurity such as phosphorus or arsenic is diffused preferably at 1 × 10 ¹⁸ cm ⁻³ or less. In the present embodiment, the N-type impurity concentration is 1 × 10 ¹⁵ cm ⁻³ or less.
In the N-type semiconductor substrate 51, the P-type semiconductor region 12 is formed on one main surface (upper surface) as described later, and then the other main surface side of the N-type semiconductor substrate 51 is cut. For this reason, the N-type semiconductor substrate 51 has a thickness obtained by adding the thickness required for the breakdown voltage set for the PN junction formed from the first N-type semiconductor region 11 and the P-type semiconductor region 12 and the thickness to be cut. It is necessary to prepare. In addition, it is necessary to provide strength required in the step of diffusing gold by heat treatment. Therefore, in the present embodiment, the N-type semiconductor substrate 51 has a thickness of about 300 μm.

Next, as shown in FIG. 2B, a P-type impurity such as boron of the second conductivity type is formed on one main surface (upper surface) of the N-type semiconductor substrate 51 using a general thermal diffusion technique. Is diffused to form a P-type semiconductor region 12. The P-type semiconductor region 12 is formed with a thickness of 10 μm and a P-type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ so that good low-resistance contact can be made with the anode electrode 31.

  Next, as shown in FIG. 2C, gold (Au) is deposited on the upper surface of the N-type semiconductor substrate 51 on which the P-type semiconductor region 12 is formed, thereby forming an Au film 53. Note that Au may be deposited on the lower surface of the N-type semiconductor substrate 51. Further, not only Au but also heavy metals such as platinum (Pt) can be used.

  A heat treatment is performed on the N-type semiconductor substrate 51 on which the Au film 53 is formed, and Au is diffused into the N-type semiconductor substrate 51. As described above, since Au has a large diffusion coefficient, it diffuses throughout the thickness direction of the N-type semiconductor substrate 51. After diffusing Au, the Au film 53 is removed.

Next, as shown in FIG. 2D, the first N-type semiconductor region 11 has a thickness required from a PN junction formed by the first N-type semiconductor region 11 and the P-type semiconductor region 12, preferably about 20 μm. The other main surface (lower surface) side of the N-type semiconductor substrate 51 is cut so that the N-type semiconductor substrate 51 is thinned.
From the above steps, the first semiconductor substrate is obtained.

Next, the manufacturing process of a 2nd semiconductor substrate is demonstrated using Fig.3 (a) and (b).
First, an N ⁺ type semiconductor substrate 52 is prepared. The N ⁺ type semiconductor substrate 52 has a thickness of about 300 μm so as to function as a support substrate. The N ⁺ type semiconductor substrate 52 has an N type impurity concentration higher than that of the first N type semiconductor region 11 and is preferably 1 × 10 ¹⁸ cm ⁻³ or more, and in this embodiment, it is formed to 1 × 10 ²⁰ cm ^−3. ing.

Next, the second N-type semiconductor region 22 is formed on the entire upper surface of the N ⁺ semiconductor substrate 52 by using an epitaxial growth method. In the present embodiment, the thickness of the second N-type semiconductor region 22 is 10 μm, the N-type impurity concentration is lower than the impurity concentration of the N ⁺ -type semiconductor substrate 52, and the N-type impurity concentration of the first N-type semiconductor region 11 is The same 1 × 10 ¹⁵ cm ⁻³ is formed.
A second semiconductor substrate is formed from the above steps.

Next, a process of fixing the first semiconductor substrate and the second semiconductor substrate and completing the diode 1 will be described with reference to FIGS.
First, as shown in FIGS. 4A and 4B, the lower surface of the N-type semiconductor substrate 51 of the first semiconductor substrate and the upper surface of the second N-type semiconductor region 22 of the second semiconductor substrate are arranged so as to overlap each other.

  Next, heat treatment is performed at about 400 ° C. to fix the lower surface of the N-type semiconductor substrate 51 of the first semiconductor substrate and the upper surface of the second N-type semiconductor region 22 of the second semiconductor substrate.

Next, as shown in FIG. 4C, the anode electrode 31 is formed on the upper surface of the P-type semiconductor region 12, and the cathode electrode 32 is formed on the lower surface of the N ⁺ -type semiconductor substrate 52 using a vacuum deposition technique.
From the above steps, the diode 1 in which Au is diffused only in the N-type semiconductor substrate 51 is obtained.

In the embodiment described above, the N-type semiconductor substrate 51 is formed until the thickness of the first N-type semiconductor region 11 is about 20 μm so that a relatively good recovery time can be obtained while lowering the operating voltage of the diode. The case of cutting and thinning and forming the thickness of the second N-type semiconductor region 22 to 10 μm has been described as an example, but it is possible to adopt a configuration different from this.
When the thickness of the first N-type semiconductor region 11 is relatively increased as compared with the second N-type semiconductor region 22, the operating voltage increases, but a short recovery time is obtained. On the other hand, when the thickness of the first N-type semiconductor region 11 is relatively decreased, the operating voltage is decreased, but the recovery time is increased. By utilizing this, even when the operating voltage is high, when a short recovery time is required, the thickness of the first N-type semiconductor region 11 can be relatively increased as compared with the present embodiment.

  By adopting the above configuration, the first semiconductor substrate in which the heavy metal is diffused and the second semiconductor substrate in which the heavy metal is not diffused can be realized so that the breakdown voltage and the switching characteristics required for the completed semiconductor element can be realized. By separately forming them and fixing them together, it is possible to provide a method for manufacturing a semiconductor element capable of distributing heavy metals in a specific region in the thickness direction of the semiconductor substrate.

In the present embodiment, since Au is diffused in the vicinity of the PN junction formed by the first N-type semiconductor region 11 and the P-type semiconductor region 12, recombination of minority carriers is favorably promoted, In the second N-type semiconductor region 22 that is a region away from the PN junction formed from the first N-type semiconductor region 11 and the P-type semiconductor region 12, Au is not diffused. In this region, the resistance is low.
As a result, it is possible to manufacture a semiconductor element with good switching characteristics and low operating voltage.

  In the above-described embodiment, the second semiconductor substrate has been described with an example in which heavy metal is not diffused. However, the present invention is not limited to this, and the steps shown in FIGS. 3A and 3B are further performed. For example, a step of forming a heavy metal film such as an Au film, a step of diffusing Au by heat treatment, and a step of removing the Au film may be added to diffuse the heavy metal at a lower concentration than the first semiconductor substrate.

  In the present embodiment, the first semiconductor substrate and the second semiconductor substrate are formed and explained by adopting a configuration in which they are fixed. However, the present invention is not limited to this, and three or more semiconductor substrates are individually formed. It is also possible to fix them.

In the above-described embodiment, the case of manufacturing a diode has been described as an example. However, the present invention is not limited to a diode, and can be applied to, for example, a bipolar transistor.
In the above-described embodiment, the N type is described as the first conductivity type and the P type is defined as the second conductivity type. However, the first conductivity type is defined as the P type and the second conductivity type is defined as the N type. Is also possible.

It is a figure which shows the structural example of the semiconductor element which concerns on embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor element which concerns on embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor element which concerns on embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor element which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Diode 11 1st N type semiconductor region 12 P type semiconductor region 21 N ⁺ type semiconductor region 22 2nd N type semiconductor region 31 Anode electrode 32 Cathode electrode 51 N type semiconductor substrate 52 N ⁺ type semiconductor substrate 53 Au film

Claims (7)

Forming a second conductivity type second semiconductor region on a surface region of one main surface of the first conductivity type first semiconductor substrate;
Diffusing heavy metal into the first semiconductor substrate;
Fixing a first conductive type second semiconductor substrate in which heavy metal is diffused at a lower concentration than in the first semiconductor substrate, or in which heavy metal is not diffused, to the other main surface of the first semiconductor substrate; The manufacturing method of the semiconductor element characterized by the above-mentioned.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the other main surface of the first semiconductor substrate is cut after the step of diffusing heavy metal.   3. The semiconductor device according to claim 1, wherein the second semiconductor substrate includes a third semiconductor region and a fourth semiconductor region fixed to the first semiconductor region of the first semiconductor substrate. Manufacturing method. 4. The semiconductor element according to claim 3, wherein impurity concentrations of the first semiconductor substrate and the fourth semiconductor region of the second semiconductor substrate are formed to be 1 × 10 ¹⁸ cm ⁻³ or less. Manufacturing method. A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type formed in a surface region of one main surface of the first semiconductor region;
A third semiconductor region of a first conductivity type formed adjacent to the other main surface of the first semiconductor region;
A first electrode electrically connected to the second semiconductor region;
A semiconductor element comprising a second electrode electrically connected to the third semiconductor region,
Heavy metal is diffused in the first semiconductor region and the second semiconductor region, and heavy metal is diffused in the third semiconductor region at a lower concentration than in the first semiconductor region and the second semiconductor region, Alternatively, a semiconductor element characterized in that heavy metal is not diffused.   The semiconductor element according to claim 5, further comprising a fourth semiconductor region between the other main surface of the first semiconductor region and the third semiconductor region. The semiconductor element according to claim 6, wherein an impurity concentration of the first semiconductor region and the fourth semiconductor region is 1 × 10 ¹⁸ cm ⁻³ or less.

Images