KR100505560B1 - A bipolar transistor having uneven structure - Google Patents
A bipolar transistor having uneven structure Download PDFInfo
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- KR100505560B1 KR100505560B1 KR1019980001010A KR19980001010A KR100505560B1 KR 100505560 B1 KR100505560 B1 KR 100505560B1 KR 1019980001010 A KR1019980001010 A KR 1019980001010A KR 19980001010 A KR19980001010 A KR 19980001010A KR 100505560 B1 KR100505560 B1 KR 100505560B1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
요철 구조를 갖는 전력 바이폴라 트랜지스터에 대해 기재되어 있다. 이 바이폴라 트랜지스터는, 반도체기판에 형성된 제1 도전형의 콜렉터영역과, 콜렉터영역 내에 형성된 제2 도전형의 베이스영역과, 베이스영역 내에 형성된 제1 도전형의 에미터영역을 구비하는 전력 반도체장치에 있어서, 에미터영역의 표면이 베이스영역의 표면보다 아래쪽에 존재하는 것을 특징으로 한다.A power bipolar transistor having an uneven structure is described. The bipolar transistor includes a power semiconductor device having a collector region of a first conductivity type formed in a semiconductor substrate, a base region of a second conductivity type formed in a collector region, and an emitter region of a first conductivity type formed in a base region. The surface of the emitter region is located below the surface of the base region.
Description
본 발명은 반도체 장치에 관한 것으로, 특히 요철구조를 갖는 전력 바이폴라 트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a power bipolar transistor having an uneven structure.
최근 응용기기의 대형화·대용량화 추세에 따라 높은 브레이크다운 전압(breakdown voltage), 높은 전류(high current) 및 고속 스위칭 특성을 갖는 전력용 반도체 소자의 필요성이 대두되고 있다. 특히, 고주파 대전력용 스위칭 소자에 적용되는 대전력용 바이폴라(bipolar) 트랜지스터는 전류 구동능력을 향상시키고 포화전압을 낮춤으로써 적용장치에서의 퍼포먼스를 향상시키는 것이 요구된다.Recently, with the trend toward larger and larger capacities of applications, the necessity of power semiconductor devices having high breakdown voltage, high current, and high speed switching characteristics is emerging. In particular, a large power bipolar transistor applied to a high frequency high power switching element is required to improve performance in an application device by improving current driving capability and lowering saturation voltage.
도 1은 종래의 전력 바이폴라 트랜지스터를 도시한 단면도로서, 도면 참조번호 "2"는 콜렉터영역을, "4"는 베이스영역을, "6"은 에미터영역을, "8"은 절연막을, "10"은 베이스전극을, "12"는 에미터전극을, 그리고 "14"는 콜렉터전극을 각각 나타낸다.1 is a cross-sectional view of a conventional power bipolar transistor, in which reference numeral "2" denotes a collector region, "4" a base region, "6" an emitter region, "8" an insulating film, and " 10 "represents a base electrode," 12 "represents an emitter electrode, and" 14 "represents a collector electrode, respectively.
도시된 바와 같이, 종래의 바이폴라 트랜지스터는 에미터영역(6)에서 콜렉터 영역(2) 사이에 있는 베이스영역(4)이 넓기 때문에, 소자의 턴-온(turn-on) 동작시 베이스영역(4)에서 캐리어(carrier)들의 재결합 확률이 높아 에미터로의 캐리어의 주입효율이 작다. 이로 인해 전류 증폭률(hFE)이 낮고 콜렉터 최대전류능력(ICmax)이 떨어지며, 소자의 턴-오프(turn-off)시 콜렉터-에미터 포화전압(Vce(sat))이 높은 문제점이 있다. As shown, the conventional bipolar transistor has a large base region 4 between the emitter region 6 and the collector region 2, so that the base region 4 during the turn-on operation of the device. ), The carrier's injection efficiency into the emitter is high because the probability of recombination of carriers is high. As a result, the current amplification factor hFE is low, the collector maximum current capability ICmax is lowered, and the collector-emitter saturation voltage Vce (sat) is high when the device is turned off.
따라서, 본 발명이 이루고자 하는 기술적 과제는, 베이스-콜렉터 내압은 감소시키지 않으면서 콜렉터 최대전류와 콜렉터-에미터 포화전압을 향상시킬 수 있는 구조의 바이폴라 트랜지스터를 제공하는 것이다.Accordingly, a technical object of the present invention is to provide a bipolar transistor having a structure capable of improving the collector maximum current and the collector-emitter saturation voltage without reducing the base-collector breakdown voltage.
상기 과제를 이루기 위하여 본 발명에 의한 바이폴라 트랜지스터는, 반도체기판에 형성된 제1 도전형의 콜렉터영역과, 상기 콜렉터영역 내에 형성된 제2 도전형의 베이스영역과, 상기 베이스영역 내에 형성된 제1 도전형의 에미터영역을 구비하는 전력 반도체장치에 있어서,In order to achieve the above object, a bipolar transistor according to the present invention includes a collector region of a first conductivity type formed in a semiconductor substrate, a base region of a second conductivity type formed in the collector region, and a first conductivity type formed in the base region. In a power semiconductor device having an emitter region,
상기 에미터영역의 표면이 베이스영역의 표면보다 아래쪽에 존재하는 것을 특징으로 한다.The surface of the emitter region is located below the surface of the base region.
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도 4는 본 발명에 의한 요철 구조를 갖는 바이폴라 트랜지스터를 도시한 단면도로서, 도면 참조번호 "22"는 콜렉터영역을, "26"은 베이스영역을, "28"은 에미터영역을, "30"은 절연막을, "32"는 베이스전극을, "34"는 에미터전극을, 그리고 "36"은 콜렉터전극을 각각 나타낸다.4 is a cross-sectional view showing a bipolar transistor having a concave-convex structure according to the present invention, wherein reference numeral 22 denotes a collector region, “26” a base region, “28” an emitter region, and “30” A silver insulating film, "32" represents a base electrode, "34" represents an emitter electrode, and "36" represents a collector electrode.
도 4를 참조하면, 베이스영역(26)에 형성된 홈의 저부에 에미터영역(28)이 형성되어 있기 때문에, 도 1에 도시된 종래의 바이폴라 트랜지스터에 비해 에미터영역(28)과 콜렉터영역(22) 사이의 거리가 매우 짧다. 따라서, 전류 증폭률이 높고 콜렉터 최대전류능력이 커지며 콜렉터-에미터 포화전압이 낮아진다. 따라서, 어떤 장치에서 동작할 때 전력의 손실이 낮아지고, 이로인해 그 시스템 장치의 퍼포먼스를 향상시킬 수 있다.4, since the emitter region 28 is formed at the bottom of the groove formed in the base region 26, the emitter region 28 and the collector region (compared to the conventional bipolar transistor shown in FIG. 22) The distance between them is very short. Thus, the current amplification factor is high, the collector maximum current capability is increased, and the collector-emitter saturation voltage is lowered. Thus, the loss of power when operating in a device can be lowered, thereby improving the performance of the system device.
도 2 내지 도 4는 본 발명에 의한 요철 구조를 갖는 바이폴라 트랜지스터의 제조방법을 설명하기 위한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of manufacturing a bipolar transistor having an uneven structure according to the present invention.
도 2를 참조하면, 제1 도전형, 예컨대 n형의 불순물이 저농도로 도우프된 콜렉터영역(22)이 형성된 반도체 기판상에, 예컨대 산화막을 형성한 후 통상의 사진식각 공정을 적용하여 상기 산화막을 패터닝함으로써, 베이스영역을 형성하기 위한 마스크층(24)을 형성한다. 상기 저농도의 콜렉터영역(22)은 잘 알려진 바와 같이, 확산 또는 에피택셜(epitaxial) 방법을 사용하여 형성할 수 있다. Referring to FIG. 2, an oxide film is formed on a semiconductor substrate on which a collector region 22 in which a first conductivity type, for example, n-type impurities are lightly doped, is formed, for example, and then subjected to a conventional photolithography process. By patterning the mask layer 24, a mask layer 24 for forming the base region is formed. The low concentration collector region 22 may be formed using a diffusion or epitaxial method, as is well known.
다음에, 상기 베이스용 마스크층(24)을 사용하여 상기 저농도(n_) 콜렉터영역(22) 내에 제2 도전형, 예컨대 보론(B; Boron)과 같은 p형의 불순물을 고농도로 이온 주입한 후 열처리함으로써 베이스영역(26)을 형성한다. 상기 열처리 공정에 의해 반도체 기판 상에는 산화막이 성장되어 필드영역과 액티브영역에서의 산화막의 두께가 다르게 된다.Next, a high concentration of p-type impurities such as boron (B), such as boron (B), is implanted into the low concentration (n_) collector region 22 using the base mask layer 24. The base region 26 is formed by heat treatment. By the heat treatment process, an oxide film is grown on the semiconductor substrate so that the thickness of the oxide film in the field region and the active region is different.
도 3을 참조하면, 사진식각 공정을 적용하여 상기 산화막을 패터닝하여 에미터영역이 형성될 영역의 반도체 기판을 노출시키는 에미터용 마스크층을 형성한다. 다음에, 상기 에미터용 마스크층을 식각 마스크로 사용하여 노출된 반도체기판, 즉 베이스영역의 일부를 실리콘 식각액을 사용하여 식각함으로써 상기 베이스영역(26)에 홈을 형성한다. 다음에, 상기 에미터용 마스크를 이용하여 인(P)과 같은 n형의 불순물을 고농도로 이온 주입한 후 열처리함으로써, 상기 베이스영역(26) 내에 에미터영역(28)을 형성한 다음, 상기 에미터용 마스크를 제거하고 결과물의 전면에 절연막(30)을 형성한다. Referring to FIG. 3, the oxide layer is patterned by using a photolithography process to form an emitter mask layer exposing a semiconductor substrate in a region where an emitter region is to be formed. Next, a groove is formed in the base region 26 by etching part of the exposed semiconductor substrate, that is, the base region using the emitter mask layer as an etching mask, using a silicon etchant. Next, a high concentration of ion implanted n-type impurities such as phosphorus (P) is used for the emitter mask, followed by heat treatment to form an emitter region 28 in the base region 26. The mask for the rotor is removed and the insulating film 30 is formed on the entire surface of the resultant.
도 4를 참조하면, 상기 절연막(30)을 부분적으로 식각하여 베이스영역(26) 및 에미터영역(28)의 일부를 노출시킨다. 다음, 결과물의 전면에 금속막을 증착한 후 이를 패터닝함으로써 베이스전극(32) 및 에미터전극(34)을 형성한 다음, 콜렉터영역(22)의 후면에 금속막을 형성하여 콜렉터전극(36)을 형성한다.Referring to FIG. 4, the insulating layer 30 is partially etched to expose a portion of the base region 26 and the emitter region 28. Next, a base film 32 and an emitter electrode 34 are formed by depositing and patterning a metal film on the entire surface of the resultant, and then forming a metal film on the rear surface of the collector region 22 to form the collector electrode 36. do.
상술한 본 발명에 의한 요철형 구조를 갖는 바이폴라 트랜지스터에 따르면, 에미터영역(28)의 표면이 베이스영역(26)의 표면보다 아래쪽에 존재하기 때문에, 에미터영역(28)과 콜렉터영역(22) 사이의 거리가 매우 짧다. 따라서, 전류 증폭률이 높고 콜렉터 최대전류능력이 커지며 콜렉터-에미터 포화전압이 낮아진다. 따라서, 어떤 장치에서 동작할 때 전력의 손실이 낮아지고, 이로인해 장치의 퍼포먼스(performance)를 향상시킬 수 있다.According to the bipolar transistor having the concave-convex structure according to the present invention described above, since the surface of the emitter region 28 exists below the surface of the base region 26, the emitter region 28 and the collector region 22. ) The distance between is very short. Thus, the current amplification factor is high, the collector maximum current capability is increased, and the collector-emitter saturation voltage is lowered. Thus, the loss of power when operating in a device can be lowered, thereby improving the performance of the device.
도 1은 종래의 전력 바이폴라 트랜지스터를 도시한 단면도이다.1 is a cross-sectional view showing a conventional power bipolar transistor.
도 2 내지 도 4는 본 발명에 의한 요철 구조를 갖는 바이폴라 트랜지스터의 제조방법을 설명하기 위한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of manufacturing a bipolar transistor having an uneven structure according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
2, 22.....콜렉터영역 4, 26.....베이스영역2, 22 ..... collector area 4, 26 ..... base area
6, 28.....에미터영역 8, 30.....절연막6, 28 ... Emitter area 8, 30 ... Insulation film
10, 32....베이스전극 12, 34....에미터전극10, 32 ... base electrode 12, 34 ... emitter electrode
14, 36....콜렉터전극14, 36 ... collector electrodes
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980001010A KR100505560B1 (en) | 1998-01-15 | 1998-01-15 | A bipolar transistor having uneven structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980001010A KR100505560B1 (en) | 1998-01-15 | 1998-01-15 | A bipolar transistor having uneven structure |
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| KR19990065625A KR19990065625A (en) | 1999-08-05 |
| KR100505560B1 true KR100505560B1 (en) | 2006-04-21 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4701998A (en) * | 1985-12-02 | 1987-10-27 | International Business Machines Corporation | Method for fabricating a bipolar transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4701998A (en) * | 1985-12-02 | 1987-10-27 | International Business Machines Corporation | Method for fabricating a bipolar transistor |
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